公开(公告)号：JP2008009982A

公开(公告)日：2008-01-17

申请号：JP2007166028

申请日：2007-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEN-YEHUDA SHMUEL ,  SATRAN JULIAN ,  SHIMONY ILAN ,  MACHULSKY ZORIK ,  LEAH SHALEV ,  KRIEGER ORRAN YAAKOV ,  XENIDIS JAMES ,  GUTHRIDGE D SCOTT

IPC: G06F12/10 ,  G06F13/28

CPC classification number: G06F12/1081 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/1044

Abstract: PROBLEM TO BE SOLVED: To provide a method and system for memory address conversion and pinning.
SOLUTION: The method includes attaching a memory address space identifier to a direct memory access (DMA) request, the DMA request is sent by a consumer and using a virtual address in a given address space. The method further includes looking up for the memory address space identifier to find a translation of the virtual address in the given address space used in the DMA request to a physical page frame. Provided that the physical page frame is found, pinning the physical page frame as long as the DMA request is in progress to prevent an unmapping operation of the virtual address in the given address space, and completing the DMA request, wherein the steps of attaching, looking up and pinning are centrally controlled by a host gateway.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供用于存储器地址转换和钉扎的方法和系统。 解决方案：该方法包括将存储器地址空间标识符附加到直接存储器访问（DMA）请求，DMA请求由消费者发送并且使用给定地址空间中的虚拟地址。 该方法还包括查找存储器地址空间标识符以找到在DMA请求中使用的给定地址空间中的虚拟地址到物理页面帧的转换。 只要找到物理页面帧，只要DMA请求正在进行，固定物理页面帧，以防止给定地址空间中虚拟地址的解映射操作，并完成DMA请求，其中附加， 查找和固定由主机网关集中控制。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2005100405A

公开(公告)日：2005-04-14

申请号：JP2004276674

申请日：2004-09-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AGUILAR MAXIMINO JR ,  CHENEN CHOU ,  DAY MICHAEL NORMAN ,  GOWEN MICHAEL STAN ,  MARK RICHARD NATTER ,  XENIDIS JAMES

IPC: G06F9/54 ,  G06F9/445

CPC classification number: G06F9/44557 ,  G06F9/44526

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for loading software on a plurality of processors. SOLUTION: A processing unit (PU) retrieves a file from a system memory and loads the file on the internal memory of the processing unit. The PU extracts a processor type from the header of the file. It is distinguished whether the file should be executed in, the PU or a synergistic processing unit (SPU) depending on its processor type. When the file should be executed in the SPU, the PU DMA (Direct Memory Access)-transfers the file to the SPU for execution. In one embodiment, the file is a combined file including both of a PU code and an SPU code. In the embodiment, the PU identifies one section header or a plurality of section headers included in the file. The section header(s) indicates the SPU code incorporated into the combined file. In the embodiment, the PU extracts the SPU code from the combined file and DMA-transfers the extracted code to the SPU for execution. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于在多个处理器上加载软件的系统和方法。 解决方案：处理单元（PU）从系统存储器检索文件，并将文件加载到处理单元的内部存储器上。 PU从文件的标题中提取处理器类型。 根据其处理器类型，区分是否应该执行文件，PU或协同处理单元（SPU）。 当文件应在SPU中执行时，PU DMA（直接内存访问） - 将文件传输到SPU执行。 在一个实施例中，该文件是包括PU代码和SPU代码两者的组合文件。 在本实施例中，PU识别文件中包括的一个部分标题或多个部分标题。 段标题表示并入组合文件中的SPU代码。 在本实施例中，PU从组合文件中提取SPU代码，DMA将提取的代码传送到SPU执行。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2006049740A3

公开(公告)日：2006-08-10

申请号：PCT/US2005034460

申请日：2005-09-23

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM ,  TOSHIBA KK

Inventor： CHOW ALEX CHUNGHEN ,  DAY MICHAEL NORMAN ,  GOWEN MICHAEL STAN ,  INOUE KEISUKE ,  XENIDIS JAMES ,  UCHIKAWA TAKAYUKI

IPC: G06F9/445

CPC classification number: G06F8/54 ,  G06F9/4425

Abstract: The present invention is a method for integrating multiple object codes from heterogeneous architectures. For a program on a first processor to reference a program from the name space of a second processor, the object code for the second-processor program is enclosed in a wrapper to create object code in the first-processor name space. The header of the wrapped object code defines a new symbol in the name space of the first processor, and the symbol points to the second-processor object code contained in the wrapped object code. Instead of directly referencing the second-processor object code, the referencing program on the first processor references the wrapped object code. A system tool can be used to wrap the object code which runs on the second processor.

Abstract translation: 本发明是用于集成来自异构体系结构的多个目标代码的方法。 对于第一个处理器上的程序从第二个处理器的名称空间引用程序，第二个处理器程序的目标代码封装在包装器中，以在第一个处理器名称空间中创建目标代码。 包装目标代码的头文件在第一个处理器的名称空间中定义一个新符号，该符号指向包含在包装目标代码中的第二个处理器目标代码。 第一处理器上的引用程序不是直接引用第二处理器对象代码，而是引用包装的对象代码。 系统工具可以用来包装在第二个处理器上运行的目标代码。

公开(公告)号：CA2577865A1

公开(公告)日：2006-04-06

申请号：CA2577865

申请日：2005-08-24

Applicant: IBM

Inventor： NUTTER MARK RICHARD ,  DAY MICHAEL NORMAN ,  AGUILAR MAXIMINO JR ,  XENIDIS JAMES

IPC: G06F12/10 ,  G06F12/02

Abstract: A system and method for virtualization of processor resources is presented. A thread is created on a processor and the processor's local memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by other processors, regardless of whether the processor is running. Additional threads create additional local memory mappings into the effective address space. The effective address space corresponds to either a physical local memory or a "soft" copy area. When the processor is running, a different processor may access data that is located in the first processor's local memory from the processor's local storage area. When the processor is not running, a softcopy of the processor's local memory is stored in a memory location (i.e. locked cache memory, pinned system memory, virtual memory, etc.) for other processors to continue accessing.

公开(公告)号：MX2007003679A

公开(公告)日：2007-04-19

申请号：MX2007003679

申请日：2005-08-24

Applicant: IBM

Inventor： DAY MICHAEL NORMAN ,  NUTTER MARK RICHARD ,  XENIDIS JAMES ,  AGUILAR MAXIMINO JR

IPC: G06F12/00

Abstract: Se presentan un sistema y un metodo para la virtualizacion de recursos de procesador. Se crea una linea sobre un procesador y la memoria local del procesador se trazo en un espacio de direccion efectivo. Al hacer esto asi. La memoria local del procesador es accesible por otros procesadores, sin importar si el procesador esta funcionando. Las lineas adicionales crean trazos de mapas de memorias locales adicionales en el espacio de direccion efectiva. Los espacios de direccion efectiva corresponden a una memoria local fisica o un area de copia "flexible". Cuando el procesador este funcionando, un procesador diferente puede tener acceso a los datos que se localizan en la memoria local del primer procesador desde el area de almacenamiento local de procesador. Cuando el procesador no esta funcionando, se almacena una copia flexible de la memoria local del procesador en lugar de la memoria (es decir, antememoria bloqueada, memoria fija del sistema, memoria virtual, etc.) para que otros procesadores continuen teniendo acceso.

公开(公告)号：CA2577865C

公开(公告)日：2011-09-27

申请号：CA2577865

申请日：2005-08-24

Applicant: IBM

Inventor： AGUILAR MAXIMINO JR ,  DAY MICHAEL NORMAN ,  NUTTER MARK RICHARD ,  XENIDIS JAMES

IPC: G06F12/10 ,  G06F12/02

Abstract: In a system and method for virtualization of processor resources, a thread is created on a processor and the processor's local memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by other processors, regardless of whether the processor is running. Additional threads create additional local memory mappings into the effective address space. The effective address space corresponds to either a physical local memory or a "soft" copy area. When the processor is running, a different processor may access data that is located in the first processor's local memory from the processor's local storage area. When the processor is not running, a softcopy of the processor's local memory is stored in a memory location (i.e. locked cache memory, pinned system memory, virtual memory, etc.) for other processors to continue accessing.

公开(公告)号：BRPI0515920A2

公开(公告)日：2009-08-04

申请号：BRPI0515920

申请日：2005-08-24

Applicant: IBM

Inventor： AGUILAR MAXIMINO JR ,  DAY MICHAEL NORMAN ,  NUTTER MARK RICHARD ,  XENIDIS JAMES

IPC: G06F12/10 ,  G06F12/02

Abstract: A system and method for virtualization of processor resources is presented. A thread is created on a processor and the processor's local memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by other processors, regardless of whether the processor is running. Additional threads create additional local memory mappings into the effective address space. The effective address space corresponds to either a physical local memory or a "soft" copy area. When the processor is running, a different processor may access data that is located in the first processor's local memory from the processor's local storage area. When the processor is not running, a softcopy of the processor's local memory is stored in a memory location (i.e. locked cache memory, pinned system memory, virtual memory, etc.) for other processors to continue accessing.