公开(公告)号：JPS63168737A

公开(公告)日：1988-07-12

申请号：JP28565187

申请日：1987-11-13

Applicant: IBM

Inventor： BAUGE MICHEL ,  MOLLIER PIERRE ,  YAMOUR YIANNIS JOHN ,  BOUDON GERARD ,  PETER JEAN-LUC

IPC: G06F11/18 ,  G06F11/16

公开(公告)号：DE3688139T2

公开(公告)日：1993-10-07

申请号：DE3688139

申请日：1986-12-30

Applicant: IBM

Inventor： BAUGE MICHEL ,  MOLLIER PIERRE ,  YAMOUR YIANNIS JOHN ,  BOUDON GERARD ,  PETER JEAN-LUC

IPC: G06F11/18 ,  G06F11/16 ,  G06F13/40

Abstract: Duplicated circuit arrangement comprising a main processor (30) and its P bit data bus (44), and two identical redundant devices (21 ; 22), each device is comprised of a processing element (23 ; 35) performing the same task in parallel on a P bits word, and send/receive circuits (24,25;36,37) controlled by the main processor through lines (SR11 to SR22) to transmit said word to and from said main processor. For each device, the send/receive circuits are split into two parts. Send/receive circuit of the first device (21) is split in two parts (24, 25); the first part (24) handles the P/2 Most Significant Bits (MSB's) and the second part (25) handles the P/2 Less Significant Bits (LSB's). In normal operation, during the transmission step, only the first part (24) is allowed to send bits on one half (33) of the data bus (44). Symmetrically send/receive circuit of the second device (22), is also split in two parts (36, 37); the first section (36) handles the P/2 Most Significant bits (MSB's) and the second part (37) handles the P/2 Less Significant Bits (LSB's); only the second part (37) is allowed to send bits on the other half (34) of the data bus (44). Therefore, the data bus driving effort is equally shared between the two devices, the maximum number of simultaneous switching is P/2 for each device. This reduction allows greater transmission speed on large busses.

公开(公告)号：DE3688139D1

公开(公告)日：1993-04-29

申请号：DE3688139

申请日：1986-12-30

Applicant: IBM

Inventor： BAUGE MICHEL ,  MOLLIER PIERRE ,  YAMOUR YIANNIS JOHN ,  BOUDON GERARD ,  PETER JEAN-LUC

IPC: G06F11/18 ,  G06F11/16 ,  G06F13/40

Abstract: The duplicated circuit arrangement has at least two devices provided with drivers connected between the outputs of a processor and the lines of the device bus. The driving effort on the p bit mash data bus is shared so that each device transmits only a part of the p bit word. The transmitted part of the p bit word consists of a set of bits corresp. to the content of a determined section of the processor. The whole p bit word is available in integrality on the p bit mash data bus, where the sets of bits supplied by the two devices are reassembled.