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    DECODING AND SELECTION CIRCUIT FOR MONOLITHIC MEMORY
    5.
    发明专利
    DECODING AND SELECTION CIRCUIT FOR MONOLITHIC MEMORY 未知

    公开(公告)号：DE3070584D1

    公开(公告)日：1985-06-05

    申请号：DE3070584

    申请日：1980-09-26

    Applicant: IBM ,  IBM FRANCE

    Inventor： BOUDON GERARD ,  DENIS BERNARD ,  DE GRIVEL VIRGINIE ,  MOLLIER PIERRE

    IPC: G11C11/41 ,  G11C11/413 ,  G11C11/415 ,  G11C16/08 ,  G11C17/18 ,  G11C11/40 ,  G11C11/24 ,  G11C17/00

    Abstract: A word line selection circuit includes a conventional Schottky diode decoder and a driver transistor which is connected to a word line. A word line is selected when the transistor is conductive and all associated diodes of the decoder are off. The base current of the driver transistor is defined by a control transistor whose conductivity is opposite to that of the driver transistor and which applies the selection current to the base of the driver transistor. A regulating transistor forms a current mirror with the control transistor to regulate the selection current. A compensation circuit associated with the regulating transistor modulates the collector current of the regulating transistor as a function of the driver transistor factor.

    6.
    发明专利
    未知

    公开(公告)号：DE3684478D1

    公开(公告)日：1992-04-23

    申请号：DE3684478

    申请日：1986-12-30

    Applicant: IBM

    Inventor： BONNEAU MARTINE ,  LE GARREC JEAN-CLAUDE ,  WALLART FRANK ,  BOUDON GERARD ,  MOLLIER PIERRE

    IPC: H03K3/3562 ,  H03K3/356

    Abstract: Disymmetry is produced in the DC mode by increased pmpedance connected in series with the second stage of the latch cell. The series impedances (R31,R32) are connected in the path for parasitic currents between the positive voltage source (Vdd) and earth (Gnd). When the data input (Do) is at logic one, the path to earth from the voltage source of parasitic current is through the first series resistance (R31) and transistor devices (P36,N33,N32). The first series resistance is embodied as a P-type transistor device (P38) of which the gate is earthed.

    7.
    发明专利
    未知

    公开(公告)号：DE3688139T2

    公开(公告)日：1993-10-07

    申请号：DE3688139

    申请日：1986-12-30

    Applicant: IBM

    Inventor： BAUGE MICHEL ,  MOLLIER PIERRE ,  YAMOUR YIANNIS JOHN ,  BOUDON GERARD ,  PETER JEAN-LUC

    IPC: G06F11/18 ,  G06F11/16 ,  G06F13/40

    Abstract: Duplicated circuit arrangement comprising a main processor (30) and its P bit data bus (44), and two identical redundant devices (21 ; 22), each device is comprised of a processing element (23 ; 35) performing the same task in parallel on a P bits word, and send/receive circuits (24,25;36,37) controlled by the main processor through lines (SR11 to SR22) to transmit said word to and from said main processor. For each device, the send/receive circuits are split into two parts. Send/receive circuit of the first device (21) is split in two parts (24, 25); the first part (24) handles the P/2 Most Significant Bits (MSB's) and the second part (25) handles the P/2 Less Significant Bits (LSB's). In normal operation, during the transmission step, only the first part (24) is allowed to send bits on one half (33) of the data bus (44). Symmetrically send/receive circuit of the second device (22), is also split in two parts (36, 37); the first section (36) handles the P/2 Most Significant bits (MSB's) and the second part (37) handles the P/2 Less Significant Bits (LSB's); only the second part (37) is allowed to send bits on the other half (34) of the data bus (44). Therefore, the data bus driving effort is equally shared between the two devices, the maximum number of simultaneous switching is P/2 for each device. This reduction allows greater transmission speed on large busses.

    8.
    发明专利
    未知

    公开(公告)号：DE68926045D1

    公开(公告)日：1996-04-25

    申请号：DE68926045

    申请日：1989-07-26

    Applicant: IBM

    Inventor： BOUDON GERARD

    IPC: H03M1/74 ,  H03K3/286 ,  H03K19/086 ,  H03K19/173 ,  H03K19/21

    Abstract: The present logic circuit family is derived from the conventional DCCS logic circuit family. The logic circuit shown in the attached drawing is a six-input AND/NAND. It includes: a logic tree (41) comprised of bottom, middle, and top stages (44, 45, 46) cascoded and dotted at the tree output nodes (OUT, OUT) to perform a determined logic function (F, F). The top stage (46) includes a current switch (49) formed by a pair of input transistors (TX431, TX432) connected in a differential amplifier configuration. The base of one input transistor (TX431) on the left side of the tree is connected to the output of an AND gate, which consists of input diodes (D431, D432, ...) and resistor (RD41). True (IN PHASE) logic input signals (Z41, Z42, ...) are ANDed in this AND gate and a first elementary output signal, is available at the common emitter node (CN43) of the said differential pair. On the right side, additional input transistors (TX433, ...) are paralleled with the other input transistor (TX432) of the differential pair, so that the complementary (OUT OF PHASE) input signals (Z41, Z42, ...) that drive the transistors, are ORed to deliver a second elementary output signal, complementary to said first elementary output signal, on said common emitter node (CN43). Same principle applies at the the first and second levels to build the bottom (44) and middle (45) stages. The present invention allows to increase the number of logical inputs to be applied to a DCCS logic circuit, and in turn, the number of logic functions performed in the logic DCCS tree. As a result, an extended library of DCCS logic circuits may be obtained.

    9.
    发明专利
    未知

    公开(公告)号：DE3688139D1

    公开(公告)日：1993-04-29

    申请号：DE3688139

    申请日：1986-12-30

    Applicant: IBM

    Inventor： BAUGE MICHEL ,  MOLLIER PIERRE ,  YAMOUR YIANNIS JOHN ,  BOUDON GERARD ,  PETER JEAN-LUC

    IPC: G06F11/18 ,  G06F11/16 ,  G06F13/40

    Abstract: The duplicated circuit arrangement has at least two devices provided with drivers connected between the outputs of a processor and the lines of the device bus. The driving effort on the p bit mash data bus is shared so that each device transmits only a part of the p bit word. The transmitted part of the p bit word consists of a set of bits corresp. to the content of a determined section of the processor. The whole p bit word is available in integrality on the p bit mash data bus, where the sets of bits supplied by the two devices are reassembled.

    10.
    发明专利
    未知

    公开(公告)号：DE3788132D1

    公开(公告)日：1993-12-16

    申请号：DE3788132

    申请日：1987-12-01

    Applicant: IBM

    Inventor： BOUDON GERARD ,  ONG IENG ,  MOLLIER PIERRE

    IPC: H03K19/08 ,  H03K19/013 ,  H03K19/017 ,  H03K19/0944 ,  H03K19/21 ,  H03K19/094

    Abstract: A multi base 2 input Bi-CMOS NAND circuit (30) is provided wherein an output node OUT connected to an output terminal (33) is coupled between pull up (31) and pull down (32) blocks. According to the present invention, the pull up block (31) is comprised of 2 identical basic cells, each comprised of a CMOS inverter (C31, C32) driving a NPN pull up transistor (T31, T32) mounted as an emitter follower. Logic signals (A31, A32) are applied on the inputs of the inverters (C31, C32), and the inverted signal (A31, A32) is available at the emitter of the emitter follower which corresponds to the output of the cell. All emitters are tied altogether to perform an OR function and are connected to said output terminal (33). As standard, the pull down block (32) includes a logic stack (34) is comprised of 2 FETS (F31, F32) serially connected between said output node OUT and a discharge device such as a feedback NFET (Z), the gate of which is connected to said output node OUT. These 2 FETS are driving a NPN pull down transistor (T), the collector of which is also connected to the output node OUT.

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