中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.019 seconds)

    3.
    发明专利
    未知

    公开(公告)号：IT8026399D0

    公开(公告)日：1980-12-03

    申请号：IT2639980

    申请日：1980-12-03

    Applicant: IBM

    Inventor： TERMAN LEWIS MADISON ,  YEE YEN SUNG

    IPC: G11C27/04 ,  G11C11/56 ,  G11C19/36 ,  H01L21/339 ,  H01L29/762 ,  G11C

    Abstract: A digital-to-analog conversion (DAC) circuit (32) and trigger comparator (34) combination is described for encoding and decoding charge packets in a common-well multi-level signal charge-coupled memory device (CCD). The DAC circuit, which may be of the weighted capacitor type, is used to generate a staircase waveform and to create the common-well under a first gate (14) in the CCD. The trigger comparator adjacent to a second gate (16) in the CCD is a detection circuit which stays in one binary state until an input charge signal is received, whereupon it switches state, In particular, the weighted capacitor DAC contains an extra offset bit which is used in the analog-to-digital or regeneration operation such that when the trigger comparator (34) switches state, the digital input to the DAC (32) at that time correctly represents the signal charge being converted. In one embodiment a circular serial-parallel-serial memory structure (37) is employed as the multi-level CCD memory system.

Patent Agency Ranking