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    MULTICHANNEL MODEM AND ITS UTILIZATION IN A PROCESS AND SYSTEM FOR TESTING A COMMUNICATION NETWORK WITH SEVERAL LEVELS
    1.
    发明专利
    MULTICHANNEL MODEM AND ITS UTILIZATION IN A PROCESS AND SYSTEM FOR TESTING A COMMUNICATION NETWORK WITH SEVERAL LEVELS 未知

    公开(公告)号：DE3069082D1

    公开(公告)日：1984-10-04

    申请号：DE3069082

    申请日：1980-11-28

    Applicant: IBM ,  IBM FRANCE

    Inventor： CHOLAT-NAMY JEAN ,  HUON SIMON ,  THIRION PHILIPPE

    IPC: H04L5/22 ,  H04J3/14 ,  H04L69/40 ,  H04L11/12

    Abstract: 1. A multiport modem of the type comprising several input/output interfaces (7A-7D) that may respectively receive the bits of several data sub channels, multiplexing means (42, 45-46, 56) for multiplexing together the data bits received through those of the interfaces which are active to form a single train of bits in accordance with a multiplexing configuration, and transmitter means (75) for sending said train of bits over a transmission channel, characterized in that it includes : means (36) for detecting a test request received from one of the interfaces, means (30) responsive to a test request to generate a test configuration code identifying the interface that supplied said test request, means (11) responsive to said test configuration code to cause said multiplexing means to assume a test configuration such that only that interface which received the detected test request will be active, storage means (73) for storing a test command received at the interface that received the test request, said command including an indication of the test to be performed and a link level identifier, decoder means (74) for decoding said link level identifier, and means (67, 73) for applying the received test command and the test configuration code to said transmitter means for transmission over said channel if said link level identifier indicates a link level other than that which includes the modem.

    2.
    发明专利
    未知

    公开(公告)号：FR2335109A1

    公开(公告)日：1977-07-08

    申请号：FR7538562

    申请日：1975-12-09

    Applicant: IBM FRANCE

    Inventor： THIRION PHILIPPE

    IPC: H04L27/38 ,  H04L27/00 ,  H04L27/22 ,  H04L27/233

    Abstract: A statistical data detection method for use in a synchronous data transmission system employing either phase modulation, combined amplitude and phase modulation or quadrature amplitude modulation. The signal space diagram of the possible states of the transmitted signal and their influence zones is divided into N elementary squares. Since the squares are rather coarse to save storage space, many such squares belong to more than one influence zone. The influence zone of a state Z defines the region within which the received signal, P, will lie when state Z has been transmitted.

    3.
    发明专利
    未知

    公开(公告)号：FR2413712A1

    公开(公告)日：1979-07-27

    申请号：FR7739966

    申请日：1977-12-30

    Applicant: IBM FRANCE

    Inventor： EPENOY GABRIEL ,  KUHNE ROLAND ,  LAURENT BERNARD ,  THIRION PHILIPPE

    IPC: G06F7/53 ,  G06F7/48 ,  G06F7/506 ,  G06F7/508 ,  G06F7/527 ,  G06F7/533 ,  G06F7/544 ,  G06F17/16 ,  G06F7/38

    Abstract: A specialized processor capable of computing a sum of products S= SIGMA +/-Pi where every product Pi is the product of two n-bit complex operands Ai+j Bi, the multiplier, and Ci+j Di, the multiplicand, where j= 2ROOT -1. The processor includes an instruction storage, means for decoding instructions read out of said storage and for controlling the operation of the processor, a data storage, and a multiplication and accumulation unit which has two multiplier-accumulator devices and several buffers for storing the operands Ai, Bi, Ci and Di sequentially read out of data storage. The real part Ai and the imaginary part Bi of the multiplier are respectively applied to the Multiplier inputs of the multiplier-accumulator devices and the real part Ci of the multiplicand is applied to the Multiplicand inputs of the multiplier-accumulator devices, which simultaneously compute the products Ai Ci and Bi Ci. The imaginary part Di of the multiplicand is then applied to the Multiplicand inputs of the multiplier-accumulator devices. The first of these then computes the product Bi Di and adds the same to the product Ai Ci, while the second device computes the product Ai Di and adds the same to the product Bi Ci to simultaneously provide the real and imaginary parts of the product Pi.

    MULTIPORT MODEM AND THE USE THEREOF IN A METHOD AND A SYSTEM FOR TESTING A MULTILEVEL COMMUNICATION NETWORK
    4.
    发明专利
    MULTIPORT MODEM AND THE USE THEREOF IN A METHOD AND A SYSTEM FOR TESTING A MULTILEVEL COMMUNICATION NETWORK 未知

    公开(公告)号：CA1172330A

    公开(公告)日：1984-08-07

    申请号：CA389262

    申请日：1981-11-02

    Applicant: IBM

    Inventor： CHOLAT-NAMY JEAN ,  HUON SIMON ,  THIRION PHILIPPE

    IPC: H04L5/22 ,  H04J3/14 ,  H04L69/40 ,  H04J3/02

    Abstract: MULTIPORT MODEM AND THE USE THEREOF IN A METHOD AND A SYSTEM FOR TESTING A MULTILEVEL COMMUNICATION NETWORK A method of testing a communication network that comprises first and second multiport modems communicating with each other through a transmission channel. Each of said modems is provided with a number of input/output interfaces and each of the interfaces on either modem is associated with a corresponding interface on the other modem. In accordance with the method of the present invention, a test request is applied to one of the interfaces on the first multiport modem, which responds thereto by generating a test configuration code identifying that interface. This modem is then caused to assume a so-called test configuration, in which only that interface to which the test request was applied is active, and a test command comprising an indication of the test to be performed and a link level identifier is applied to that interface. If the identifier designates the link level to which the first modem belongs, this modem will control the test specified in the test command. If another link level is designated then the test command and the test configuration code will both be sent to the second multiport modem. The second modem will then decode the link level identifier and, if the link level so designated is not the one to which is pertains, will assume a test configuration such that only the interface associated with the first modem interface which received the test request will be active, and the test command will be applied to that active interface. In accordance with another aspect of the invention the test configuration code also identifies the bit rate associated with the test command. The invention also provides a test system that implements the above method. The invention further provides an improved multiport modem to be used in conjunction with the test method and system mentioned above. FR9-79-013

    METHOD AND ARRANGEMENT FOR INITIATING AN ADAPTIVE EQUALIZER STARTING FROM AN UNKNOWN DATA SIGNAL IN A TRANSMISSION SYSTEM UTILIZING QUADRATURE AMPLITUDE MODULATION
    6.
    发明专利
    METHOD AND ARRANGEMENT FOR INITIATING AN ADAPTIVE EQUALIZER STARTING FROM AN UNKNOWN DATA SIGNAL IN A TRANSMISSION SYSTEM UTILIZING QUADRATURE AMPLITUDE MODULATION 未知

    公开(公告)号：DE2967301D1

    公开(公告)日：1985-01-03

    申请号：DE2967301

    申请日：1979-05-07

    Applicant: IBM

    Inventor： GODARD DOMINIQUE ,  THIRION PHILIPPE

    IPC: H04B3/06 ,  H03H11/04 ,  H04L25/03 ,  H04L27/38 ,  H04L27/00

    Abstract: A method and a device for training the equalizer of a receiver used in a QAM transmission system, by means of an unknown data signal, thereby enabling in particular said equalizer to be trained in the cases described above. In accordance with the method of the present invention, in a data receiver wherein, under normal operating conditions, the data is detected with respect to a first constellation, the equalizer is trained by detecting the data with respect to a second constellation which comprises fewer points than said first constellation and by adjusting the coefficients of the equalizer by means of an error signal produced as a result of the detection operation performed with respect to the second constellation. In accordance with a first embodiment of the present invention, the second constellation is comprised of those points of the first constellation that are farthest from its center. In accordance with a second embodiment of the invention, the points of the second constellation are obtained as follows: the first constellation is divided into L sets of points Sl, l=1, 2, . . . , L and a point bl of the second constellation is associated with each set Sl in accordance with the relation where the ak's are those points of the first constellation that belong to the set Sl.

    7.
    发明专利
    未知

    公开(公告)号：DE2855722A1

    公开(公告)日：1979-07-12

    申请号：DE2855722

    申请日：1978-12-22

    Applicant: IBM

    Inventor： EPENOY GABRIEL IRENEE ,  KUHNE ROLAND ,  LAURENT BERNARD ,  THIRION PHILIPPE

    IPC: G06F7/53 ,  G06F7/48 ,  G06F7/506 ,  G06F7/508 ,  G06F7/527 ,  G06F7/533 ,  G06F7/544 ,  G06F17/16 ,  G06F7/52

    Abstract: A specialized processor capable of computing a sum of products S= SIGMA +/-Pi where every product Pi is the product of two n-bit complex operands Ai+j Bi, the multiplier, and Ci+j Di, the multiplicand, where j= 2ROOT -1. The processor includes an instruction storage, means for decoding instructions read out of said storage and for controlling the operation of the processor, a data storage, and a multiplication and accumulation unit which has two multiplier-accumulator devices and several buffers for storing the operands Ai, Bi, Ci and Di sequentially read out of data storage. The real part Ai and the imaginary part Bi of the multiplier are respectively applied to the Multiplier inputs of the multiplier-accumulator devices and the real part Ci of the multiplicand is applied to the Multiplicand inputs of the multiplier-accumulator devices, which simultaneously compute the products Ai Ci and Bi Ci. The imaginary part Di of the multiplicand is then applied to the Multiplicand inputs of the multiplier-accumulator devices. The first of these then computes the product Bi Di and adds the same to the product Ai Ci, while the second device computes the product Ai Di and adds the same to the product Bi Ci to simultaneously provide the real and imaginary parts of the product Pi.

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