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    Making trench capacitor in semiconductor substrate employs series of partial collars, fillings and self-adjusting masking to achieve high aspect ratio
    1.
    发明专利
    Making trench capacitor in semiconductor substrate employs series of partial collars, fillings and self-adjusting masking to achieve high aspect ratio 未知

    公开(公告)号：DE10358599B3

    公开(公告)日：2005-06-23

    申请号：DE10358599

    申请日：2003-12-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHOLZ ARND ,  GOLDBACH MATTHIAS

    IPC: H01L21/8242

    Abstract: A trench (2) is formed in the substrate (1). Its wall (21) is formed by a first collar (41) in the lower trench section (2'). In the central- and upper trench sections (2'', 2''') it is formed by the substrate. The trench is provided with a capacitor dielectric (51). A lower region (2'-A) of the lower trench zone is provided with a first filling (61). The trench wall above this first filling, including the central trench section, is provided with a second collar (42). The trench is filled with a second filling (62) above the first, including the central trench section. A trench (2) is formed in the substrate (1). Its wall (21) is formed by a first collar (41) in the lower trench section (2'). In the central- and upper trench sections (2'', 2''') it is formed by the substrate. The trench is provided with a capacitor dielectric (51). A lower region (2'-A) of the lower trench zone is provided with a first filling (61). The trench wall above this first filling, including the central trench section, is provided with a second collar (42). The trench is filled with a second filling above the first, including the central trench section. A second vertical part of the trench (23) is covered with a self-adjusting mask, with a first vertical part (22) of the trench remaining uncovered. The second collar in the first vertical partial trench (22) is removed. The self-adjusting mask and second filling are removed. The bare capacitor dielectric in the first vertical partial trench is removed. The trench is filled with a contacting filling to form a trenched contact between substrate (1) and first filling, through the contacting filling.

    2.
    发明专利
    未知

    公开(公告)号：DE10240406A1

    公开(公告)日：2003-06-05

    申请号：DE10240406

    申请日：2002-09-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHOLZ ARND ,  DEV PRAKASH C

    IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

    Abstract: A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide layer under the pad nitride layer, and a recessed gate poly in the trench. The method further includes depositing a spacer material on the oxide liner, removing exposed portions of the oxide layer from the semiconductor, and depositing a poly stud material over the semiconductor wherein the spacer material is encapsulated in poly stud material. The method includes polishing the semiconductor to the top trench oxide layer, and etching the top trench oxide layer.

    4.
    发明专利
    未知

    公开(公告)号：DE10317601A1

    公开(公告)日：2003-12-04

    申请号：DE10317601

    申请日：2003-04-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HUMMLER KLAUS ,  SCHOLZ ARND

    IPC: H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

    Abstract: A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133) and trench capacitor top surfaces (131). A second assist layer (136) is disposed over the first assist layer (134). The second assist layer (136) is removed from over the trench capacitor top surface (131), and the first assist layer (134) is removed from the trench capacitor top surface (131) using the second assist layer (136) as a mask. The second assist layer (136) is removed, and a first insulating layer (140) is disposed over the first assist layer (134) and trench capacitor top surface (131). A second insulating layer (142) is disposed over the first insulating layer (140), and the second insulating layer (142) is removed from the trench sidewalls (133). The first insulating layer (140) and the first assist layer (134) are removed from the trench sidewalls (133). The TTI layer (148) comprises the first and second insulating layer portions (146/144) that are left remaining over the trench capacitors (118). The TTI layer (148) has a greater thickness over the trench capacitor inner regions (152) than over the trench capacitor outer regions (150).

    6.
    发明专利
    未知

    公开(公告)号：DE10245105A1

    公开(公告)日：2003-05-15

    申请号：DE10245105

    申请日：2002-09-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHOLZ ARND

    IPC: H01L21/8242

    Abstract: In a process for manufacturing deep trench (32) memory cells, a method of enhancing the process window by better protecting the nitride spacer (52) prior to the process of stripping the pad nitride layer (38). The method also provides for the deposition of a nitride liner (64) and offers an additional advantage of not requiring the top shoulder (58) of the nitride spacer (52) to be over etched during its formation.

    7.
    发明专利
    未知

    公开(公告)号：DE10317601B4

    公开(公告)日：2008-04-03

    申请号：DE10317601

    申请日：2003-04-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HUMMLER KLAUS ,  SCHOLZ ARND

    IPC: H01L21/8242 ,  H01L21/20 ,  H01L21/334 ,  H01L27/108

    Abstract: A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133) and trench capacitor top surfaces (131). A second assist layer (136) is disposed over the first assist layer (134). The second assist layer (136) is removed from over the trench capacitor top surface (131), and the first assist layer (134) is removed from the trench capacitor top surface (131) using the second assist layer (136) as a mask. The second assist layer (136) is removed, and a first insulating layer (140) is disposed over the first assist layer (134) and trench capacitor top surface (131). A second insulating layer (142) is disposed over the first insulating layer (140), and the second insulating layer (142) is removed from the trench sidewalls (133). The first insulating layer (140) and the first assist layer (134) are removed from the trench sidewalls (133). The TTI layer (148) comprises the first and second insulating layer portions (146/144) that are left remaining over the trench capacitors (118). The TTI layer (148) has a greater thickness over the trench capacitor inner regions (152) than over the trench capacitor outer regions (150).

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