公开(公告)号：JP2002050701A

公开(公告)日：2002-02-15

申请号：JP2001197112

申请日：2001-06-28

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： THOMAS W DAYER ,  LOUIS L SHEW ,  DAVID L KOTEKI ,  KARL J REEDENSU ,  GERHARD KUNKEL ,  LI HONG ,  YOUNG LIM ,  YON JIN PAKU

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM cell which eliminates critical photolithorgraphic fabrication steps by merging stacked capacitor construction with electrical contacts, and to provide a method of fabrication thereof. SOLUTION: It is sufficient to conduct in one lithography step to form electrical contacts, because the stacked capacitors are on the same plane as bit lines and the stacked capacitors are located in a insulating material provided between the bit lines. Unlike the conventional capacitor-over-bit line(COB) DRAM cells having the capacitors on the bit lines, this DRAM cell having capacitors adjacent to the bit lines eliminates the need to have dedicated contacts in the capacitor, making it possible to realize higher capacitance with lower global topography.