公开(公告)号：JPH10143366A

公开(公告)日：1998-05-29

申请号：JP29417897

申请日：1997-10-27

Applicant: IBM ,  MOTOROLA INC

Inventor： AFSAR MUHAMMAD NURAL ,  JESSANI ROMESH MANGHO ,  MALLICK SOUMMYA ,  MCDONALD ROBERT GREG ,  SHARMA MUKESH

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system to implement analyzing mechanism depending on early data in a high performance data processing system utilizing command issuance which is not in program order. SOLUTION: A command cache 14 is provided with plural cache lines and the respective cache lines are capable of storing plural commands. A register depending cache 44 contains the same number of cache lines as the command cache 14 and the respective cache lines in the register depending cache 44 are capable of storing the same number of register depending units as the commands in respective cache lines in the command cache 14. Groups of the register depending units are fetched from the register depending cache 44 in a single processor cycle.

公开(公告)号：GB2320775B

公开(公告)日：2001-07-11

申请号：GB9721623

申请日：1997-10-14

Applicant: IBM ,  MOTOROLA INC

Inventor： AFSAR MUHAMMAD NURAL ,  JESSANI ROMESH MANGHO ,  MALLICK SOUMMYA ,  MCDONALD ROBERT GREG ,  SHARMA MUKESH

IPC: G06F9/38

公开(公告)号：GB2320775A

公开(公告)日：1998-07-01

申请号：GB9721623

申请日：1997-10-14

Applicant: IBM ,  MOTOROLA INC

Inventor： AFSAR MUHAMMAD NURAL ,  JESSANI ROMESH MANGHO ,  MALLICK SOUMMYA ,  MCDONALD ROBERT GREG ,  SHARMA MUKESH

IPC: G06F9/38

Abstract: To implement an early data dependency resolution mechanism for a high-performance data processing system that utilises out-of-order instruction issue, an instruction cache and a register-dependency cache are provided. The instruction cache has multiple cache lines each capable of storing multiple instructions 50. The register-dependency cache contains an identical number of cache lines each capable of storing an identical number of register-dependency units 52 as there are instructions in each of the cache lines within the instruction cache. In a single processor cycle, a group of register-dependency units 52 are fetched from the register-dependency cache. All register-dependency units that have no forward data dependency within the group of register-dependency units are identified and translated to its respective instruction utilising a corresponding cache line within the instruction cache. All of the translated instructions are issued within a next processor cycle. Since each register-dependency unit 52 has fewer bits than an instruction 50, more of them can be fetched per processor cycle.