公开(公告)号：JPH10143366A

公开(公告)日：1998-05-29

申请号：JP29417897

申请日：1997-10-27

Applicant: IBM ,  MOTOROLA INC

Inventor： AFSAR MUHAMMAD NURAL ,  JESSANI ROMESH MANGHO ,  MALLICK SOUMMYA ,  MCDONALD ROBERT GREG ,  SHARMA MUKESH

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system to implement analyzing mechanism depending on early data in a high performance data processing system utilizing command issuance which is not in program order. SOLUTION: A command cache 14 is provided with plural cache lines and the respective cache lines are capable of storing plural commands. A register depending cache 44 contains the same number of cache lines as the command cache 14 and the respective cache lines in the register depending cache 44 are capable of storing the same number of register depending units as the commands in respective cache lines in the command cache 14. Groups of the register depending units are fetched from the register depending cache 44 in a single processor cycle.

公开(公告)号：GB2320775B

公开(公告)日：2001-07-11

申请号：GB9721623

申请日：1997-10-14

Applicant: IBM ,  MOTOROLA INC

Inventor： AFSAR MUHAMMAD NURAL ,  JESSANI ROMESH MANGHO ,  MALLICK SOUMMYA ,  MCDONALD ROBERT GREG ,  SHARMA MUKESH

IPC: G06F9/38

公开(公告)号：GB2320775A

公开(公告)日：1998-07-01

申请号：GB9721623

申请日：1997-10-14

Applicant: IBM ,  MOTOROLA INC

Inventor： AFSAR MUHAMMAD NURAL ,  JESSANI ROMESH MANGHO ,  MALLICK SOUMMYA ,  MCDONALD ROBERT GREG ,  SHARMA MUKESH

IPC: G06F9/38

Abstract: To implement an early data dependency resolution mechanism for a high-performance data processing system that utilises out-of-order instruction issue, an instruction cache and a register-dependency cache are provided. The instruction cache has multiple cache lines each capable of storing multiple instructions 50. The register-dependency cache contains an identical number of cache lines each capable of storing an identical number of register-dependency units 52 as there are instructions in each of the cache lines within the instruction cache. In a single processor cycle, a group of register-dependency units 52 are fetched from the register-dependency cache. All register-dependency units that have no forward data dependency within the group of register-dependency units are identified and translated to its respective instruction utilising a corresponding cache line within the instruction cache. All of the translated instructions are issued within a next processor cycle. Since each register-dependency unit 52 has fewer bits than an instruction 50, more of them can be fetched per processor cycle.

公开(公告)号：JP2000029701A

公开(公告)日：2000-01-28

申请号：JP11990699

申请日：1999-04-27

Applicant: IBM

Inventor： MCDONALD ROBERT GREG

IPC: G06F9/38 ,  G06F12/08

Abstract: PROBLEM TO BE SOLVED: To obtain a system for taking discontinuous blocks of instructions in a data processing system by allowing an auxiliary cache means to overlay 2nd instructions, when 1st instructions are branches to the 2nd instructions. SOLUTION: When 1st instructions have the branches to 2nd instructions, the auxiliary cache means overlays the 2nd instructions. In this system, a branch history table(BHT) 104 receives a BHT update signal and outputs a read signal. The read signal from the BHT 104 is supplied to a branching logic 116. An instruction cache 106 receives a write signal from an external supply source, such as an L2 cache. The instruction cache 106 outputs 8 instructions to the branching logic 116. An address-0 signal is supplied directly to the branching logic 116. The branching logic 116 supplies an override address signal to a multiplexer 120.

公开(公告)号：JP2001117770A

公开(公告)日：2001-04-27

申请号：JP2000304842

申请日：2000-10-04

Applicant: IBM

Inventor： MCDONALD ROBERT GREG ,  PEICHUN PETER RYUU ,  OLSON CHRISTOPHER HANS

IPC: G06F9/34 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To efficiently process plural out-of-order, speculative and optional updates for a register. SOLUTION: The register 200 includes at least one register bit and can include one or more sticky bits 201. An executing unit 204 is suitable for executing one set of computer instructions 202. A temporary result buffer 206 is constituted so as to receive register bit modification information provided by an instruction from the executing unit 204. The temporary result buffer 206 is suitable for storing the modification information in a pair of set /clear bits corresponding to individual register bits of the register. A committing function circuit is constituted so as to receive the pair of set/clear bits from the temporary result buffer 206 when the instruction is committed. The committing function circuit generates the updated bit in response to reception of the pair of set/clear bits.

公开(公告)号：GB2360375B

公开(公告)日：2004-03-31

申请号：GB0023163

申请日：2000-09-20

Applicant: IBM

Inventor： MCDONALD ROBERT GREG ,  LIU PEICHUN PETER ,  OLSON CHRISTOPHER HANS

IPC: G06F9/34 ,  G06F9/38

公开(公告)号：CA2317080A1

公开(公告)日：2001-04-14

申请号：CA2317080

申请日：2000-08-28

Applicant: IBM

Inventor： LIU PEICHUN PETER ,  OLSON CHRISTOPHER HANS ,  MCDONALD ROBERT GREG

IPC: G06F9/34 ,  G06F9/38 ,  G06F9/30 ,  G06F9/312 ,  G06F9/318

Abstract: A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bi t modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The update d bit is then committed to the corresponding register bit of the register.

公开(公告)号：GB2360375A

公开(公告)日：2001-09-19

申请号：GB0023163

申请日：2000-09-20

Applicant: IBM

Inventor： MCDONALD ROBERT GREG ,  LIU PEICHUN PETER ,  OLSON CHRISTOPHER HANS

IPC: G06F9/34 ,  G06F9/38

Abstract: An execution unit 204 is provided for out-of-order execution of a set of instructions 202 and outputs register bit modification information to a temporary result buffer 206 which is suitable for storing the register bit modification information 208 corresponding to an instruction in set/clear pairs (213, Fig. 7) of bits. A register 200 includes at least one register bit and may include sticky bits 201 each bit corresponding to respective set/clear pairs of the register bit modification information. A commit function circuit (209, fig 3/4) is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed and generating an updated bit. The updated bit is then committed to the corresponding register bit of the register.

公开(公告)号：DE69929936T2

公开(公告)日：2006-08-24

申请号：DE69929936

申请日：1999-04-19

Applicant: IBM

Inventor： MCDONALD ROBERT GREG

IPC: G06F9/38 ,  G06F12/08

Abstract: A method and apparatus for obtaining non-contiguous blocks of instruction in a data processing system is disclosed. The apparatus comprises an instruction cache means for providing a first plurality of instructions and branch logic means for receiving the first plurality of instructions and for providing branch history information about the first plurality of instructions. The apparatus further includes an auxiliary cache means for receiving a second plurality of instructions based upon the branch history information. The auxiliary cache means overlays at least a one of the second plurality of instructions if there is a branch in the first plurality of instructions and the branch is to the second plurality of instructions. Thus the apparatus can use branch history information and an auxiliary cache to fetch multiple noncontiguous groups of instructions in a single cycle. Furthermore, the technique allows noncontiguous fetching to be performed without requiring multiple levels of nested branch prediction logic to be evaluated in a single cycle.

公开(公告)号：DE69929936D1

公开(公告)日：2006-04-27

申请号：DE69929936

申请日：1999-04-19

Applicant: IBM

Inventor： MCDONALD ROBERT GREG

IPC: G06F9/38 ,  G06F12/08

Abstract: A method and apparatus for obtaining non-contiguous blocks of instruction in a data processing system is disclosed. The apparatus comprises an instruction cache means for providing a first plurality of instructions and branch logic means for receiving the first plurality of instructions and for providing branch history information about the first plurality of instructions. The apparatus further includes an auxiliary cache means for receiving a second plurality of instructions based upon the branch history information. The auxiliary cache means overlays at least a one of the second plurality of instructions if there is a branch in the first plurality of instructions and the branch is to the second plurality of instructions. Thus the apparatus can use branch history information and an auxiliary cache to fetch multiple noncontiguous groups of instructions in a single cycle. Furthermore, the technique allows noncontiguous fetching to be performed without requiring multiple levels of nested branch prediction logic to be evaluated in a single cycle.