公开(公告)号：CA2680597A1

公开(公告)日：2009-12-23

申请号：CA2680597

申请日：2009-10-16

Applicant: IBM CANADA

Inventor： ARCHAMBAULT ROCH G ,  CHEN TONG ,  GAO YAOQING ,  SURA ZEHRA ,  SILVERA RAUL E ,  MOHAMMED KHALED ,  PEKHIMENKO GENNADY ,  O'BRIEN JOHN K

IPC: G06F9/44 ,  G06F9/46

Abstract: An illustrative embodiment provides a computer-implemented process for managing speculative assist threads for data pre-fetching that analyzes collected source code and cache profiling information to identify a code region containing a delinquent load instruction and generates an assist thread, including a value for a local version number, at a program entry point within the identified code region. Upon activation of the assist thread the local version number of the assist thread is compared to the global unique version number of the main thread for the identified code region and an iteration distance between the assist thread relative to the main thread is compared to a predefined value. The assist thread is executed when the local version number of the assist thread matches the global unique version number of the main thread, and the iteration distance between the assist thread relative to the main thread is within a predefined range of values.

公开(公告)号：CA2680597C

公开(公告)日：2011-06-07

申请号：CA2680597

申请日：2009-10-16

Applicant: IBM CANADA

Inventor： ARCHAMBAULT ROCH G ,  CHEN TONG ,  GAO YAOQING ,  MOHAMMED KHALED ,  O'BRIEN JOHN K ,  PEKHIMENKO GENNADY ,  SILVERA RAUL E ,  SURA ZEHRA

IPC: G06F9/44 ,  G06F9/46

Abstract: An illustrative embodiment provides a computer-implemented process for managing speculative assist threads for data pre-fetching that analyzes collected source code and cache profiling information to identify a code region containing a delinquent load instruction and generates an assist thread, including a value for a local version number, at a program entry point within the identified code region. Upon activation of the assist thread the local version number of the assist thread is compared to the global unique version number of the main thread for the identified code region and an iteration distance between the assist thread relative to the main thread is compared to a predefined value. The assist thread is executed when the local version number of the assist thread matches the global unique version number of the main thread, and the iteration distance between the assist thread relative to the main thread is within a predefined range of values.

公开(公告)号：CA2680601C

公开(公告)日：2010-11-02

申请号：CA2680601

申请日：2009-10-16

Applicant: IBM CANADA

Inventor： CHEN TONG ,  GAO YAOQING

IPC: G06F12/02 ,  G06F12/0862 ,  G06F9/46 ,  G06F12/0811

Abstract: An illustrative embodiment provides a computer-implemented process for managing multiple speculative assist threads for data pre-fetching that sends a command from an assist thread of a first processor to second processor and a memory, wherein parameters of the command specify a processor identifier of the second processor, responsive to receiving the command, reply by the second processor indicating an ability to receive a cache line that is a target of a pre-fetch, responsive to receiving the command replying by the memory indicating a capability to provide the cache line, responsive to receiving replies from the second processor and the memory, sending, by the first processor, a combined response to the second processor and the memory, wherein the combined response indicates an action, and responsive to the action indicating a transaction can continue sending the requested cache line, by the memory, to the second processor into a target cache level on the second processor.

公开(公告)号：CA2680601A1

公开(公告)日：2009-12-23

申请号：CA2680601

申请日：2009-10-16

Applicant: IBM CANADA

Inventor： CHEN TONG ,  GAO YAOQING

IPC: G06F12/02 ,  G06F12/0862 ,  G06F9/46 ,  G06F12/0811

Abstract: An illustrative embodiment provides a computer-implemented process for managing multiple speculative assist threads for data pre-fetching that sends a comma nd from an assist thread of a first processor to second processor and a memory, wherein parameters of the command specify a processor identifier of the second processor, responsive t o receiving the command, reply by the second processor indicating an ability to receive a cache line that is a target of a pre-fetch, responsive to receiving the command replying by the memory indicating a capability to provide the cache line, responsive to receiving replies from t he second processor and the memory, sending, by the first processor, a combined response to the second processor and the memory, wherein the combined response indicates an action, and responsive to the action indicating a transaction can continue sending the requested cache line, by t he memory, to the second processor into a target cache level on the second processor.