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公开(公告)号:DE2756764A1
公开(公告)日:1979-06-21
申请号:DE2756764
申请日:1977-12-20
Applicant: IBM DEUTSCHLAND
Inventor: BLUM ARNOLD DIPL ING , BAZLEN DIETER DR ING , BERGER ROLF DIPL ING , BOCK DIETRICH DIPL ING , CHILINSKI HERBERT DIPL ING , GENG HELLMUTH ROLAND , GETZLAFF KLAUS ING GRAD , HAJDU JOHANN , RICHTER STEPHAN
Abstract: The synchronising arrangement is for a processor and memory in an electronic data processing installation. There is a delay from the memory when data is demanded from it by the processor. A section of the arrangement has an output to the operations register of the processor for the provision of a code combination corresponding to a certain micro-instruction lasting for the duration of the memory delay. The operations decoder provides a corresponding output signal which stops the demand cycle counter. The operations register loads the next operation code existing at its input when it receives the next pulse of the system.
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公开(公告)号:DE2758146A1
公开(公告)日:1979-06-28
申请号:DE2758146
申请日:1977-12-27
Applicant: IBM DEUTSCHLAND
Inventor: BLUM ARNOLD DIPL ING , CHILINSKI HERBERT DIPL ING , GENG HELLMUTH ROLAND , GETZLAFF KLAUS ING GRAD , HAJDU JOHANN , NEUBER SIEGFRIED , RICHTER STEPHAN , RUST BERND , WILLE UDO ING GRAD
Abstract: A control switching network is used in the programming circuit of a digital calculator. The processing unit is connected to a process timing and control unit. This unit is connected to a data store via a set of the intermediate connections. A system is used to keep the store in synchronism with the processing unit. An identification network is used, which produces a signal controlling the action of the store. Store activity monitoring signals are used, and instructions are given to the store in a series of given cycles.
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