公开(公告)号：DE1234055B

公开(公告)日：1967-02-09

申请号：DEJ0026818

申请日：1964-11-05

Applicant: IBM DEUTSCHLAND

Inventor： ABERNATHY ROGER EDWIN ,  GENG ROLAND ,  ONWILER WALTER NEWTON ,  TARANTO ROBERT

IPC: G06F7/49 ,  G06F7/50

Abstract: 1,083,838. Digital computers. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 22, 1965 [Nov. 5, 1964], No. 44751/65. Heading G4A. In an electric digital system for adding or subtracting numbers in a pair of registers R, L, Fig. 2, in which the contents of each is successively incremented or decremented until a carry takes place in one indicating that the result is in the other, the contents of at least one of the registers is initially compared with zero and the radix whereby the registers L, R to be incremented or decremented are chosen in order to obtain a minimum number of steps. The example of Fig. 2 is applied to registers R, L having four binary bits (radix 16), but binary coded decimal system is referred to. The registers R, L form single digit components of multi-order registers (Fig. 3, not shown) and to which the process is applied to each order stage sequentially. The contents of the registers are first tested for zero, thereby stopping further operation and indicating directly, when one operand is zero, that the other register contains the result. The contents, if non-zero, are then compared at V to determine which is nearer to zero or to the radix B as by comparison with B/2, whereby control circuit A-S-ST is set to operate the incrementing, decrementing circuit M to selectively operate on the registers R, L until a carry is indicated in registers UR, UL. In the event of the result being in the register other than that in which it is required, the circuit (M2) (Figs. 3 or 4, not shown) is used to transfer the contents to the required register. In the modification of (Fig. 4, not shown) the contents of only one register (R) is compared with B/2. A detailed circuit (Fig. 9, not shown) illustrates a system for incrementing or decrementing the registers by gating oppositely phased timing pulses (R1), (R3), the operation continuing until a carry is indicated in registers (UR), (UL).

公开(公告)号：DE1263088B

公开(公告)日：1968-03-14

申请号：DEJ0027782

申请日：1965-03-26

Applicant: IBM DEUTSCHLAND

Inventor： SCHELER TITUS ,  GENG ROLAND ,  KUNDEL GERHARD ,  HODGES PAUL ,  UTLEY BRIAN GEORGE

IPC: G11C21/00

公开(公告)号：DE2264752A1

公开(公告)日：1975-02-06

申请号：DE2264752

申请日：1972-10-02

Applicant: IBM DEUTSCHLAND

Inventor： BLUM ARNOLD DIPL ING ,  MOHR CLAUS DR ING ,  REICHL LEOPOLD DIPL ING ,  SONNTAG GUENTER DIPL ING ,  GENG ROLAND ,  IRRO FRITZ DIPL ING

IPC: G06F11/10 ,  G06F11/14

Abstract: The receiver determines a transmission error by means of parity testing circuits. When there is an error present, an error indication is stored automatically. The defective data element is given a parity corresponding to the defective information by means of a generator circuit. The data block is then transmitted completely and after transmission the error indication is requested by the control microprogramme. When the errors have appeared, the data block is transmitted once more.