公开(公告)号：DE2553517A1

公开(公告)日：1977-06-08

申请号：DE2553517

申请日：1975-11-28

Applicant: IBM DEUTSCHLAND

Inventor： CLEMEN RAINER DIPL ING ,  HAUG WERNER DIPL ING ,  SCHNADT ROBERT DIPL PHYS DR

IPC: G11C5/00 ,  G11C27/02 ,  H03H7/30 ,  H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03K5/133 ,  H03K5/153 ,  H03K17/28

Abstract: Utilization of a chip internal clock driver, for capacitive loads such as MOS circuits, which provides in response to an external clock phase adjustable and delayed secondary clock pulses. The delay circuit is an inverter circuit which uses a precharged coupling capacitor whose potential is dynamically increased (boosted) by capacitive coupling the input pulse to approximately twice the supply voltage and which capacitor is subsequently discharged by a constant current thus defining a delay time in a more extended and more precise range.