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公开(公告)号：DE2340814A1
公开(公告)日：1975-03-06
申请号：DE2340814
申请日：1973-08-11
Applicant: IBM DEUTSCHLAND
IPC: G11C5/00 , G11C8/18 , G11C11/34 , G11C11/415 , G11C11/417 , G11C11/418 , H03M7/00 , G11C8/00
Abstract: For each binary position of the coded addresses the selection device shows a phase splitter whose two outputs are connected to associated inputs of decoders. In order to increase the noise resistance jointly clocked AND gates are inserted at the inputs and outputs of the phase splitters, and at the outputs of the decoders.
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公开(公告)号：DE2824727A1
公开(公告)日：1979-12-13
申请号：DE2824727
申请日：1978-06-06
Applicant: IBM DEUTSCHLAND
IPC: G11C11/417 , G11C7/00 , G11C11/40 , G11C11/412 , H01L27/02 , H03K3/356
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公开(公告)号：DE2243671A1
公开(公告)日：1974-03-28
申请号：DE2243671
申请日：1972-09-06
Applicant: IBM DEUTSCHLAND
Inventor： BAITINGER UTZ DIPL ING DR , HAUG WERNER DIPL ING , ILLI MANFRED DIPL ING DR , REMSHARDT ROLF DIPL ING DR
IPC: G11C11/413 , G11C11/407 , H03K19/017 , H03K19/094 , H03K17/04
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Patent Agency Ranking
公开(公告)号：DE2935465A1
公开(公告)日：1981-03-19
申请号：DE2935465
申请日：1979-09-01
Applicant: IBM DEUTSCHLAND
IPC: H03K5/00 , H03K5/02 , H03K19/0185 , H03K19/094 , H03K19/08
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公开(公告)号：DE2553517A1
公开(公告)日：1977-06-08
申请号：DE2553517
申请日：1975-11-28
Applicant: IBM DEUTSCHLAND
IPC: G11C5/00 , G11C27/02 , H03H7/30 , H03H11/26 , H03K5/00 , H03K5/13 , H03K5/133 , H03K5/153 , H03K17/28
Abstract: Utilization of a chip internal clock driver, for capacitive loads such as MOS circuits, which provides in response to an external clock phase adjustable and delayed secondary clock pulses. The delay circuit is an inverter circuit which uses a precharged coupling capacitor whose potential is dynamically increased (boosted) by capacitive coupling the input pulse to approximately twice the supply voltage and which capacitor is subsequently discharged by a constant current thus defining a delay time in a more extended and more precise range.
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公开(公告)号：DE2838817A1
公开(公告)日：1980-03-20
申请号：DE2838817
申请日：1978-09-06
Applicant: IBM DEUTSCHLAND
IPC: G11C11/41 , G11C11/24 , G11C11/408 , G11C11/413 , H03K3/353 , H03K3/356 , H03K5/02 , H03K5/15 , H03K19/0185 , H03K5/00 , G11C11/40
Abstract: Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.
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公开(公告)号：DE2460150A1
公开(公告)日：1976-06-24
申请号：DE2460150
申请日：1974-12-19
Applicant: IBM DEUTSCHLAND
IPC: G11C11/411 , H01L21/8229 , H01L27/07 , H01L27/102 , G11C11/40
Abstract: A semiconductor storage circuit for use in monolithic memories. The circuit is comprised of a storage cell coupled to input-output bit lines through active devices having symmetrical conduction properties. The storage cell can be comprised of a pair of cross coupled bipolar transistors having resistors as collector load devices. Schottky field effect transistors (MESFET's) are active devices having symmetrical conduction properties.
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公开(公告)号：DE2232274A1
公开(公告)日：1974-01-31
申请号：DE2232274
申请日：1972-06-30
Applicant: IBM DEUTSCHLAND
Inventor： BAITINGER UTZ DIPL ING DR , FRANTZ HERMANN , HAUG WERNER DIPL ING , ILLI MANFRED DIPL ING DR , KELLER GUENTER DIPL ING
IPC: G11C11/412 , G05F3/24 , G11C11/407 , G11C11/417 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L1/24
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