公开(公告)号：FR2443101A1

公开(公告)日：1980-06-27

申请号：FR7834432

申请日：1978-11-30

Applicant: IBM FRANCE

Inventor： AUSTRUY PIERRE ,  DALBOUSSIERE GERARD

IPC: G06F9/46 ,  G06F13/00 ,  G06F13/362 ,  G06F13/374 ,  G06F3/04

Abstract: Adapter interfaces (ADAPT) and line driver interfaces (RDVP and RDVC) are divided into subgroups within a pyramid type of architecture. Each subgroup is provided with independent preselection means for determining the path through the pyramid from the CCU BUS to the adapter to be serviced first.

公开(公告)号：DE3272316D1

公开(公告)日：1986-09-04

申请号：DE3272316

申请日：1982-08-30

Applicant: IBM ,  IBM FRANCE

Inventor： CASTEL RENE ,  DALBOUSSIERE GERARD ,  KULAKOWSKI MICHEL

IPC: G06F11/00 ,  G06F11/07 ,  G06F13/00 ,  H04L29/00 ,  H04L29/02 ,  G06F11/22

Abstract: In a data processing equipment handling communication lines connected to a central control unit through adapters and a CCU input/output bus, an error reporting device is provided in each adapter for reporting error conditions occurring in the adapter to the central control unit. The adapters are of the type including a microcode controlled microprocessor provided with input and output buses connected to the CCU input/output bus through an interface. The error reporting device in association with dedicated circuits in the interface insures the transmission of the error conditions occurring in the adapter to the central control unit, even when such error conditions affect the integrity of the microcode. When the error reporting device detects an error affecting the microcode integrity, it generates a hard stop signal which causes the operation of the microprocessor under the control of the microcode to be stopped and the error conditions to be transferred to the central control unit making use of the same paths as those used for reporting errors which do not affect the microcode integrity.

公开(公告)号：FR2428284A1

公开(公告)日：1980-01-04

申请号：FR7817709

申请日：1978-06-07

Applicant: IBM FRANCE

Inventor： DALBOUSSIERE GERARD ,  DRAPER WILBURN D

IPC: G06F9/46 ,  G06F13/00 ,  G06F13/374

Abstract: A dynamic preselect interrupt priority circuit in which a plurality of adapters dynamically readjust priority until selected whereupon adjustment stops and the adapter having the highest interrupt and position priority is selected.