公开(公告)号：DE3272316D1

公开(公告)日：1986-09-04

申请号：DE3272316

申请日：1982-08-30

Applicant: IBM ,  IBM FRANCE

Inventor： CASTEL RENE ,  DALBOUSSIERE GERARD ,  KULAKOWSKI MICHEL

IPC: G06F11/00 ,  G06F11/07 ,  G06F13/00 ,  H04L29/00 ,  H04L29/02 ,  G06F11/22

Abstract: In a data processing equipment handling communication lines connected to a central control unit through adapters and a CCU input/output bus, an error reporting device is provided in each adapter for reporting error conditions occurring in the adapter to the central control unit. The adapters are of the type including a microcode controlled microprocessor provided with input and output buses connected to the CCU input/output bus through an interface. The error reporting device in association with dedicated circuits in the interface insures the transmission of the error conditions occurring in the adapter to the central control unit, even when such error conditions affect the integrity of the microcode. When the error reporting device detects an error affecting the microcode integrity, it generates a hard stop signal which causes the operation of the microprocessor under the control of the microcode to be stopped and the error conditions to be transferred to the central control unit making use of the same paths as those used for reporting errors which do not affect the microcode integrity.

公开(公告)号：FR2443101A1

公开(公告)日：1980-06-27

申请号：FR7834432

申请日：1978-11-30

Applicant: IBM FRANCE

Inventor： AUSTRUY PIERRE ,  DALBOUSSIERE GERARD

IPC: G06F9/46 ,  G06F13/00 ,  G06F13/362 ,  G06F13/374 ,  G06F3/04

Abstract: Adapter interfaces (ADAPT) and line driver interfaces (RDVP and RDVC) are divided into subgroups within a pyramid type of architecture. Each subgroup is provided with independent preselection means for determining the path through the pyramid from the CCU BUS to the adapter to be serviced first.

公开(公告)号：FR2428284A1

公开(公告)日：1980-01-04

申请号：FR7817709

申请日：1978-06-07

Applicant: IBM FRANCE

Inventor： DALBOUSSIERE GERARD ,  DRAPER WILBURN D

IPC: G06F9/46 ,  G06F13/00 ,  G06F13/374

Abstract: A dynamic preselect interrupt priority circuit in which a plurality of adapters dynamically readjust priority until selected whereupon adjustment stops and the adapter having the highest interrupt and position priority is selected.

公开(公告)号：CA1273122A

公开(公告)日：1990-08-21

申请号：CA535923

申请日：1987-04-29

Applicant: IBM

Inventor： COSTES MICHEL L ,  DALBOUSSIERE GERARD ,  BARKER KENNETH

IPC: G06F13/00 ,  G06F13/12 ,  H04L69/14 ,  G06F9/22 ,  G06F9/28

Abstract: The high speed line adapter comprises a bit handling layer (34,46) and a byte handling layer (36,50) and a receive queue mechanism (48). The bit layer receives the frames from the high speed line 9. It performs the SDLC protocol, it removes the flag and BCC characters and adds one ending condition control character which indicates whether the frame was correctly received or not. It causes the address and control fields, the data if any and the ending condition character to be stored into a receive queue buffer at the first free address. The byte layer 50 takes out the frame characters from the receive queue as soon as a pool buffer is available in the memory of the central unit of the communication controller. It sends the data if any to said memory through a direct access memory bus and sends the address and control fields and the ending condition to the microprocessor of the adapter. The provision of the receive queue mechanism allows high speed lines to be connected to a communication controller, without modifying its network control program.

公开(公告)号：DE2966775D1

公开(公告)日：1984-04-19

申请号：DE2966775

申请日：1979-04-23

Applicant: IBM

Inventor： DALBOUSSIERE GERARD ,  DRAPER WILBURN D

IPC: G06F9/46 ,  G06F13/00 ,  G06F13/374 ,  H04Q3/54 ,  G06F3/04

Abstract: A dynamic preselect interrupt priority circuit in which a plurality of adapters dynamically readjust priority until selected whereupon adjustment stops and the adapter having the highest interrupt and position priority is selected.

公开(公告)号：IT1165335B

公开(公告)日：1987-04-22

申请号：IT2695679

申请日：1979-10-31

Applicant: IBM

Inventor： AUSTRUY PIERRE ,  DALBOUSSIERE GERARD

IPC: G06F9/46 ,  G06F13/00 ,  G06F13/362 ,  G06F13/374 ,  G06F

Abstract: Adapter interfaces (ADAPT) and line driver interfaces (RDVP and RDVC) are divided into subgroups within a pyramid type of architecture. Each subgroup is provided with independent preselection means for determining the path through the pyramid from the CCU BUS to the adapter to be serviced first.

公开(公告)号：CA1190654A

公开(公告)日：1985-07-16

申请号：CA433749

申请日：1983-08-03

Applicant: IBM

Inventor： CASTEL RENE ,  DALBOUSSIERE GERARD ,  KULAKOWSKI MICHEL

IPC: G06F11/00 ,  G06F11/07 ,  G06F13/00 ,  H04L29/00 ,  H04L29/02 ,  G06F11/28

Abstract: A DEVICE FOR REPORTING ERROR CONDITIONS OCCURRING IN ADAPTERS TO THE DATA PROCESSING EQUIPMENT CENTRAL CONTROL UNIT In data processing equipment handling communication lines connected to a central control unit (CCU) through adapters and a CCU input/output bus, an error reporting device is provided in each adapter for reporting error conditions occuring in the adapter to the central control unit. The adapters are of the type including a microcode controlled microprocessor provided with input and output buses connected to the CCU input/output bus through an interface. The error reporting device in association with dedicated circuits in the interface insures the transmission of the error conditions occuring in the adapter to the central control unit, even when such error conditions affect the integrity of the microcode. When the error reporting device detects an error affecting the microcode integrity, it generates a hard stop signal which causes the operation of the microprocessor under the control of the microcode to be stopped and the error conditions to be transferred to the central control unit making use of the same paths as those used fro reporting errors which do not affecte the microcode integrity.

公开(公告)号：DE2963428D1

公开(公告)日：1982-09-16

申请号：DE2963428

申请日：1979-10-12

Applicant: IBM

Inventor： AUSTRUY PIERRE ,  DALBOUSSIERE GERARD

IPC: G06F9/46 ,  G06F13/00 ,  G06F13/362 ,  G06F13/374 ,  G06F3/04

Abstract: Adapter interfaces (ADAPT) and line driver interfaces (RDVP and RDVC) are divided into subgroups within a pyramid type of architecture. Each subgroup is provided with independent preselection means for determining the path through the pyramid from the CCU BUS to the adapter to be serviced first.

公开(公告)号：CA1124354A

公开(公告)日：1982-05-25

申请号：CA337678

申请日：1979-10-16

Applicant: IBM

Inventor： AUSTRUY PIERRE ,  DALBOUSSIERE GERARD

IPC: G06F9/46 ,  G06F13/00 ,  G06F13/362 ,  G06F13/374 ,  H04L11/00

Abstract: An improved system for selecting interface circuits on a priority basis and applies, in particular, to communication controllers. More particularly, the invention relates to means for controlling the transfers of data via adapters on a priority basis. The system interconnects that make requests for services at differing priority levels and contains a central processing unit including a lens characterized in that it includes dividing the interface circuits into subgroups of a first pyramid stage each provided with an asynchronous preselection of the interface circuit which has the highest priority level within each of the subgroups and an interfacer for each of the subgroups that make up the first stage using one of the interface circuits to make up a second stage of the pyramid.

公开(公告)号：DE3677007D1

公开(公告)日：1991-02-21

申请号：DE3677007

申请日：1986-04-30

Applicant: IBM

Inventor： COSTES LEON MICHEL ,  DALBOUSSIERE GERARD ,  BARKER KENNETH IBM CORPORATION

IPC: G06F13/00 ,  G06F13/12 ,  H04L69/14

Abstract: The high speed line adapter comprises a bit handling layer (34,46) and a byte handling layer (36,50) and a receive queue mechanism (48). The bit layer receives the frames from the high speed line 9. It performs the SDLC protocol, it removes the flag and BCC characters and adds one ending condition control character which indicates whether the frame was correctly received or not. It causes the address and control fields, the data if any and the ending condition character to be stored into a receive queue buffer at the first free address. The byte layer 50 takes out the frame characters from the receive queue as soon as a pool buffer is available in the memory of the central unit of the communication controller. It sends the data if any to said memory through a direct access memory bus and sends the address and control fields and the ending condition to the microprocessor of the adapter. The provision of the receive queue mechanism allows high speed lines to be connected to a communication controller, without modifying its network control program.