公开(公告)号：FR2298137A1

公开(公告)日：1976-08-13

申请号：FR7501855

申请日：1975-01-14

Applicant: IBM FRANCE

Inventor： DAUBY ALAIN ,  RODES DANIEL ROGER ,  RISO VLADIMIR

IPC: G06F7/508 ,  G06F7/52 ,  G06F7/523 ,  G06F7/48 ,  H03K19/34

公开(公告)号：FR2296221A1

公开(公告)日：1976-07-23

申请号：FR7443561

申请日：1974-12-27

Applicant: IBM FRANCE

Inventor： BORIE JEAN-CLAUDE ,  COUDER ALAIN ,  DAUBY ALAIN ,  DEMANGE MICHEL ,  LEBIZAY GERALD ,  LECHACZINSKY MICHEL

IPC: H04Q3/545 ,  G06F1/02 ,  G06F9/46 ,  G06F13/36 ,  G06F13/40 ,  G06F15/80 ,  G06F17/10 ,  H04Q11/04 ,  G06F7/00 ,  H04J6/00 ,  H04M7/00

Abstract: A modular digital signal processor based on a master-slave architecture has the capability of expanding its processing power by aggregating additional modules in a tree type structure. In such a processor the control functions are subdivided into groups, each for performance in a distinct control unit. One or more of the control units can perform a master function with respect to one or several slaved control units and can itself be a slave to a higher level control unit. The arithmetic data functions of the processor are performed in pipe line multiplier-accumulator units (PMAU), each of which is controlled by, instructions from an associated control unit.