公开(公告)号：WO2007138063A1

公开(公告)日：2007-12-06

申请号：PCT/EP2007/055211

申请日：2007-05-29

Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC) ,  UMICORE ,  LEYS, Frederik ,  BONZOM, Renaud ,  CAYMAX, Matty ,  LOO, Roger

Inventor： LEYS, Frederik ,  BONZOM, Renaud ,  CAYMAX, Matty ,  LOO, Roger

IPC: H01L21/20 ,  H01L21/205

CPC classification number: C30B29/08 ,  C30B25/20 ,  C30B29/04 ,  C30B29/06 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02634

Abstract: The invention relates to a method for improving the surface roughness of a semiconductor substrate. A method is provided for reducing the roughness of a semiconductor substrate surface comprising the steps of: providing a semiconductor substrate, the surface of which comprises a group IV mono-crystalline semiconductor material, and depositing, on said group IV mono-crystalline semiconductor material, a layer of (substantially) the same group IV mono-crystalline semiconductor material, by a deposition technique using nitrogen and/or at least one noble gas as carrier gas.

Abstract translation: 本发明涉及一种改善半导体衬底的表面粗糙度的方法。 提供了一种降低半导体衬底表面粗糙度的方法，包括以下步骤：提供半导体衬底，其表面包括IV族单晶半导体材料，并在所述IV族单晶半导体材料上沉积， 通过使用氮气和/或至少一种惰性气体作为载气的沉积技术形成（基本上）相同的IV族单晶半导体材料层。

公开(公告)号：WO2010003928A2

公开(公告)日：2010-01-14

申请号：PCT/EP2009/058529

申请日：2009-07-06

Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) ,  LOO, Roger ,  LEYS, Frederik ,  CAYMAX, Matty

Inventor： LOO, Roger ,  LEYS, Frederik ,  CAYMAX, Matty

IPC: H01L21/225 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/2254 ,  H01L21/2256 ,  H01L29/1054 ,  H01L29/66803 ,  H01L29/7842

Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.

Abstract translation: 一种用于将物质引入应变半导体层的方法，包括：提供包括第一区域和第二区域的衬底，所述第一区域包括暴露的应变半导体层，将所述衬底装载到反应室中，然后形成共形第一物质， 至少在暴露的应变半导体层上，然后进行热处理，由此使第一种类的至少一部分从第一种类层扩散到应变半导体层中，并且至少部分地激活 在应变半导体层中扩散的第一类物质。

公开(公告)号：WO2004053997A1

公开(公告)日：2004-06-24

申请号：PCT/BE2003/000213

申请日：2003-12-09

Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC) ,  ASM AMERICA INC. ,  CHEN, Jerry ,  WILMAN, Tsai ,  CAYMAX, Matty ,  MAES, Jan-Willem

Inventor： CHEN, Jerry ,  WILMAN, Tsai ,  CAYMAX, Matty ,  MAES, Jan-Willem

IPC: H01L29/43

CPC classification number: H01L21/28194 ,  C23C16/0218 ,  C23C16/308 ,  C23C16/345 ,  C23C16/405 ,  C23C16/45525 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31645 ,  H01L21/318 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting said semiconductor substrate with said high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor phase reactant in a plasma-enhanced chemical vapor deposition process (PECVD) or a plasma-enhanced atomic layer chemical vapor deposition (PE ALCVD) process. Furthermore, the present invention provides a dielectric stack in an integrated circuit comprising (i) a high-k dielectric layer comprising at least a high-k material, (ii) a dielectric layer comprising at least silicon and nitrogen; (iii) an intermediate layer disposed between said high-k dielectric layer and said dielectric layer, said intermediate layer comprising said high-k material, silicon and nitrogen.

Abstract translation: 本发明提供了一种用于在集成电路中制造电介质叠层的方法，包括以下步骤：（i）在半导体衬底上形成高k电介质层，（ii）使所述半导体衬底与所述高k电介质层对 包含气相反应物的氮和包含气相反应物的硅在等离子体增强化学气相沉积工艺（PECVD）或等离子体增强原子层化学气相沉积（PE ALCVD）工艺中。 此外，本发明提供了一种集成电路中的电介质堆叠，包括（i）至少包含高k材料的高k电介质层，（ii）至少包含硅和氮的电介质层; （iii）设置在所述高k电介质层和所述电介质层之间的中间层，所述中间层包含所述高k材料，硅和氮。

公开(公告)号：WO2015091781A2

公开(公告)日：2015-06-25

申请号：PCT/EP2014/078441

申请日：2014-12-18

Applicant: IMEC VZW ,  KATHOLIEKE UNIVERSITEIT LEUVEN

Inventor： CAYMAX, Matty ,  HEYNE, Markus

IPC: C23C16/00

CPC classification number: H01L21/02568 ,  C23C16/02 ,  C23C16/305 ,  C23C16/45553 ,  C23C16/56 ,  H01L21/02052 ,  H01L21/02068 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02488 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02661 ,  H01L21/02664

Abstract: Method of producing one or more transition metal dichalcogenide (MX 2 ) layers on a substrate, comprising the steps of: obtaining a substrate having a surface and depositing MX 2 on the surface using ALD deposition, starting from a metal halide precursor and a chalcogen source (H 2 X), at a deposition temperature of about 300°C. Suitable metals are Mo and W, suitable chalcogenides are S, Se and Te. The substrate may be (111) oriented. Also mixtures of two or more MX 2 layers of different compositions can be deposited on the substrate, by repeating at least some of the steps of the method.

Abstract translation: 在基材上制备一种或多种过渡金属二硫族元素（MX2）层的方法，包括以下步骤：从金属卤化物前体和硫族元素源（H2X）开始，使用ALD沉积获得具有表面并在表面上沉积MX2的基底 ），在约300℃的沉积温度下。 合适的金属是Mo和W，合适的硫族化合物是S，Se和Te。 衬底可以是（111）取向的。 通过重复该方法的至少一些步骤，也可以将不同组成的两个或更多个MX2层的混合物沉积在基材上。

公开(公告)号：WO2012130933A9

公开(公告)日：2012-10-04

申请号：PCT/EP2012/055620

申请日：2012-03-29

Applicant: IMEC ,  KATHOLIEKE UNIVERSITEIT LEUVEN ,  VINCENT, Benjamin ,  GENCARELLI, Federica ,  LOO, Roger ,  CAYMAX, Matty

Inventor： VINCENT, Benjamin ,  GENCARELLI, Federica ,  LOO, Roger ,  CAYMAX, Matty

IPC: H01L21/02 ,  H01L21/205

Abstract: A method is provided for depositing a monocrystalline Sn-containing semiconductor material on a substrate, comprising providing a semiconductor material precursor, a Sn precursor and a carrier gas in a chemical vapor deposition (CVD) reactor, and epitaxially growing the Sn- containing semiconductor material on the substrate, wherein the Sn precursor comprises tin tetrachloride (SnC14). SnC1 4 is used as Sn-precursor for chemical vapor deposition of Sn comprising semiconductor materials.

公开(公告)号：WO2004064130A1

公开(公告)日：2004-07-29

申请号：PCT/BE2004/000009

申请日：2004-01-14

Applicant: UNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC) ,  KRONINKLIJKE PHILIPS ELECTRONICS ,  DELHOUGNE, Romain ,  LOO, Roger ,  MEUNIER-BEILLARD, Philippe ,  CAYMAX, Matty

Inventor： DELHOUGNE, Romain ,  LOO, Roger ,  MEUNIER-BEILLARD, Philippe ,  CAYMAX, Matty

IPC: H01L21/20

CPC classification number: H01L29/107 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02667 ,  H01L29/1054

Abstract: The invention relates to a semiconductor device comprising a semiconductor substrate and having on its top at least a Thin Strain Relaxed Buffer, consisting essentially of a stack of three layers, characterized in that the Thin Strain Relaxed Buffer is not an active part of the semiconductor device and in that said three layers defining the Thin Strain Relaxed Buffer have an essentially constant Ge concentration, said three layers being: - a first epitaxial layer of Si 1-x Ge x , x being the Ge concentration; - a second epitaxial layer of Si 1-x Ge x : C on said first epitaxial layer, the amount of C being at least 0.3 %; - a third epitaxial layer of Si 1-x Ge x on said second layer.

Abstract translation: 本发明涉及一种半导体器件，其包括半导体衬底，并且在其顶部至少具有由三层叠层构成的薄应变松弛缓冲器，其特征在于薄应变弛豫缓冲器不是半导体器件的有源部分 并且所述限定薄应变松弛缓冲液的三个层具有基本上恒定的Ge浓度，所述三个层是： - Si1-xGex的第一外延层，x是Ge浓度; - 在所述第一外延层上的Si1-xGex：C的第二外延层，C的量为至少0.3％; - 所述第二层上的Si1-xGex的第三外延层。

公开(公告)号：EP2691977B1

公开(公告)日：2019-06-05

申请号：EP12714271.9

申请日：2012-03-29

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： VINCENT, Benjamin ,  GENCARELLI, Federica ,  LOO, Roger ,  CAYMAX, Matty

IPC: H01L21/205 ,  H01L31/02 ,  H01L31/048 ,  H01L31/055

公开(公告)号：EP1570525B1

公开(公告)日：2015-12-02

申请号：EP03782011.5

申请日：2003-12-09

Applicant: IMEC ,  ASM America, Inc.

Inventor： CHEN, Jerry ,  WILMAN, Tsai ,  CAYMAX, Matty ,  MAES, Jan-Willem

IPC: H01L21/316 ,  H01L29/51 ,  H01L29/49 ,  H01L29/43 ,  H01L21/318 ,  H01L21/314

CPC classification number: H01L21/28194 ,  C23C16/0218 ,  C23C16/308 ,  C23C16/345 ,  C23C16/405 ,  C23C16/45525 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31645 ,  H01L21/318 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1588408B1

公开(公告)日：2014-06-25

申请号：EP04701867.6

申请日：2004-01-14

Applicant: IMEC ,  NXP B.V.

Inventor： DELHOUGNE, Romain ,  LOO, Roger ,  MEUNIER-BEILLARD, Philippe ,  CAYMAX, Matty

IPC: H01L21/20 ,  H01L29/10

CPC classification number: H01L29/107 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02667 ,  H01L29/1054

公开(公告)号：EP1103075B1

公开(公告)日：2009-09-09

申请号：EP99928916.8

申请日：1999-07-02

Applicant: IMEC

Inventor： STALMANS, Lieven ,  POORTMANS, Jef ,  CAYMAX, Matty ,  SAID, Khalid ,  NIJS, Johan

IPC: H01L31/052 ,  H01L31/028

CPC classification number: H01L31/1804 ,  H01L31/028 ,  H01L31/0547 ,  H01L31/056 ,  H01L31/068 ,  H01L31/072 ,  Y02E10/52 ,  Y02E10/547 ,  Y02P70/521

Abstract: The present invention is related to a thin-film opto-electronic device on a conductive silicon-containing substrate (1), said device including a sequence of layers, said layers comprising at least: a layer of a porous medium (2), preferably a porous silicon, on said substrate, said porous layer having both light diffusing and light reflecting properties; a non-porous layer (3) on said porous silicon layer, with at least one first region and at least one second region being in said non-porous layer, said first region of a first conductivity type acting as a light absorber, said second region having a conductivity of a second type, different from said first conductivity type, said sequence of layers being such that optical confinement is realised in said device.