公开(公告)号：EP2365521B1

公开(公告)日：2018-12-26

申请号：EP11075009.8

申请日：2011-01-20

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven K.U. Leuven R&D

Inventor： Claes, Gert ,  Witvrouw, Ann

IPC: B81B7/00

CPC classification number: B81B7/0077 ,  B81B2207/015 ,  B81C2203/0136 ,  B81C2203/0163 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: Novel anchor designs for thin film packages are disclosed which, in a preferred embodiment are a combination of SiGe-filled trenches and Si-oxide-filled spacing. Depending on the release process, additional manufacturing process steps are to be performed in order to obtain the desired mechanical strength. For aggressive release processes, additional soft sputter etch and a Ti-TiN interlayer in the anchor region may be needed. The ratio of the total SiGe-SiGe anchor area to the SiO 2 -SiGe anchor area determines also the mechanical strength of the anchor. If this ratio is larger than 1, the thin film package reaches the MIL-standard requirements.

公开(公告)号：EP2277823A3

公开(公告)日：2013-09-11

申请号：EP10075263.3

申请日：2010-06-18

Applicant: IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

Inventor： Jain, Ajay ,  Severi, Simone ,  Claes, Gert ,  Heck, John

IPC: B81C1/00

CPC classification number: B81C1/00246 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.

公开(公告)号：EP2327658A1

公开(公告)日：2011-06-01

申请号：EP09177497.6

申请日：2009-11-30

Applicant: IMEC

Inventor： Witvrouw, Ann ,  Haspeslagh, Luc ,  Claes, Gert

IPC: B81C1/00

CPC classification number: B81C1/00293 ,  B81B2201/0264 ,  B81B2203/0315 ,  B81B2207/015 ,  B81C2203/0136 ,  B81C2203/0145 ,  B81C2203/0735 ,  B81C2203/0771

Abstract: A method is disclosed for manufacturing a sealed cavity comprised in a microelectronic device, comprising forming a sacrificial layer at least at locations where the cavity is to be provided, depositing a membrane layer on top of the sacrificial layer, patterning the membrane layer in at least two separate membrane layer blocks, removing the sacrificial laye through the membrane layer, and sealing the cavity by sealing the membrane layer, wherein patterning the membrane layer is performed after removal of the sacrificial layer; and associated microelectronic devices.

Abstract translation: 一种方法，光盘游离缺失了用于制造微电子器件包括一个密封的腔体，包括至少在所述空腔将被提供的位置形成牺牲层，在牺牲层的顶部上沉积一膜层，在图案化该薄膜层的至少 两个单独的薄膜层块，除去穿过膜层牺牲Laye的，并通过密封薄膜层，图案化worin薄膜层去除牺牲层之后，进行密封所述腔体; 和相关联的微电子器件。

公开(公告)号：EP2365521A3

公开(公告)日：2014-06-04

申请号：EP11075009.8

申请日：2011-01-20

Applicant: IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

Inventor： Claes, Gert ,  Witvrouw, Ann

IPC: B81B7/00

CPC classification number: B81B7/0077 ,  B81B2207/015 ,  B81C2203/0136 ,  B81C2203/0163 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: Novel anchor designs for thin film packages are disclosed which, in a preferred embodiment are a combination of SiGe-filled trenches and Si-oxide-filled spacing.
Depending on the release process, additional manufacturing process steps are to be performed in order to obtain the desired mechanical strength. For aggressive release processes, additional soft sputter etch and a Ti-TiN interlayer in the anchor region may be needed.
The ratio of the total SiGe-SiGe anchor area to the SiO 2 -SiGe anchor area determines also the mechanical strength of the anchor. If this ratio is larger than 1, the thin film package reaches the MIL-standard requirements.

公开(公告)号：EP2277823A2

公开(公告)日：2011-01-26

申请号：EP10075263.3

申请日：2010-06-18

Applicant: IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

Inventor： Jain, Ajay ,  Severi, Simone ,  Claes, Gert ,  Heck, John

IPC: B81C1/00

CPC classification number: B81C1/00246 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.

Abstract translation: 本公开提出了用于制造MEMS器件的硅 - 锗层，并通过该硅 - 锗层接触的层之间的低电阻接触的方法，检查作为CMOS金属层或另一种硅 - 锗层，通过对开口 在介电层叠层分离两个层。 的层间形成在该开口中，从而覆盖在该开口的底部的另一个层的暴露表面上的开口的至少侧壁上。 这个中间层可以与所述硅 - 锗层接触包括TiN层。 这个中间层可以在TiN层和层之间进一步包括Ti层被接触。 在另一个实施例该中间层包括与所述硅 - 锗层接触的氮化钽层。 该中间层然后可以进一步包括在TaN层和所述层之间的Ta层被接触。

公开(公告)号：EP2327658B1

公开(公告)日：2018-07-04

申请号：EP09177497.6

申请日：2009-11-30

Applicant: IMEC VZW

Inventor： Witvrouw, Ann ,  Haspeslagh, Luc ,  Claes, Gert

IPC: B81C1/00

CPC classification number: B81C1/00293 ,  B81B2201/0264 ,  B81B2203/0315 ,  B81B2207/015 ,  B81C2203/0136 ,  B81C2203/0145 ,  B81C2203/0735 ,  B81C2203/0771

Abstract: A method is disclosed for manufacturing a sealed cavity comprised in a microelectronic device, comprising forming a sacrificial layer at least at locations where the cavity is to be provided, depositing a membrane layer on top of the sacrificial layer, patterning the membrane layer in at least two separate membrane layer blocks, removing the sacrificial laye through the membrane layer, and sealing the cavity by sealing the membrane layer, wherein patterning the membrane layer is performed after removal of the sacrificial layer; and associated microelectronic devices.

公开(公告)号：EP2365521A2

公开(公告)日：2011-09-14

申请号：EP11075009.8

申请日：2011-01-20

Applicant: IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

Inventor： Claes, Gert ,  Witvrouw, Ann

IPC: H01L23/14

CPC classification number: B81B7/0077 ,  B81B2207/015 ,  B81C2203/0136 ,  B81C2203/0163 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: Novel anchor designs for thin film packages are disclosed which, in a preferred embodiment are a combination of SiGe-filled trenches and Si-oxide-filled spacing.
Depending on the release process, additional manufacturing process steps are to be performed in order to obtain the desired mechanical strength. For aggressive release processes, additional soft sputter etch and a Ti-TiN interlayer in the anchor region may be needed.
The ratio of the total SiGe-SiGe anchor area to the SiO 2 -SiGe anchor area determines also the mechanical strength of the anchor. If this ratio is larger than 1, the thin film package reaches the MIL-standard requirements.

Abstract translation: 公开了用于薄膜封装的新型锚定设计，其在优选实施例中是SiGe填充的沟槽和填充Si氧化物的间隔的组合。 取决于释放过程，为了获得期望的机械强度，将执行额外的制造工艺步骤。 对于侵蚀性释放方法，可能需要额外的软溅射蚀刻和锚定区域中的Ti-TiN中间层。 总SiGe-SiGe锚定面积与SiO 2 -SiGe锚定面积的比值也决定了锚的机械强度。 如果该比例大于1，则薄膜封装达到MIL标准要求。