公开(公告)号：US10424579B2

公开(公告)日：2019-09-24

申请号：US15857022

申请日：2017-12-28

Applicant: IMEC vzw

Inventor： Mirko Scholz ,  Shih-Hung Chen

IPC: H01L29/08 ,  H01L27/02 ,  H01L29/10 ,  H02H9/04 ,  H01L29/735

Abstract: A semiconductor device for electric discharge protection is disclosed. In one aspect, the semiconductor device includes a substrate having a p-type doping. The semiconductor device includes a first well and a second well having an n-type doping and arranged spaced apart within a surface layer of the substrate, and a third well having a p-type doping and arranged in the surface layer of the substrate between the first well and the second well. The semiconductor device further includes an emitter region and a base contact region having a p-type doping and arranged within a surface layer of the first well, and a collector region having a p-type doping. The collector region is arranged at least partly within a surface layer of the third well and such that it overlaps both of the first well and the second well. An integrated circuit including a semiconductor device is also provided.

公开(公告)号：US09847336B2

公开(公告)日：2017-12-19

申请号：US15245671

申请日：2016-08-24

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Geert Van der Plas ,  Mirko Scholz

IPC: H01L27/092 ,  H01L21/266 ,  H01L27/06 ,  H01L21/033 ,  H01L29/808 ,  H01L29/66 ,  H01L21/265 ,  H01L21/761 ,  H01L29/10 ,  H01L29/45 ,  H01L29/861

CPC classification number: H01L27/0928 ,  H01L21/0332 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/098 ,  H01L29/1058 ,  H01L29/456 ,  H01L29/66128 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8611

Abstract: The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

公开(公告)号：US20190206855A1

公开(公告)日：2019-07-04

申请号：US15857022

申请日：2017-12-28

Applicant: IMEC vzw

Inventor： Mirko Scholz ,  Shih-Hung Chen

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/735 ,  H02H9/04

CPC classification number: H01L27/0262 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/1095 ,  H01L29/735 ,  H02H9/046

Abstract: A semiconductor device for electric discharge protection is disclosed. In one aspect, the semiconductor device includes a substrate having a p-type doping. The semiconductor device includes a first well and a second well having an n-type doping and arranged spaced apart within a surface layer of the substrate, and a third well having a p-type doping and arranged in the surface layer of the substrate between the first well and the second well. The semiconductor device further includes an emitter region and a base contact region having a p-type doping and arranged within a surface layer of the first well, and a collector region having a p-type doping. The collector region is arranged at least partly within a surface layer of the third well and such that it overlaps both of the first well and the second well. An integrated circuit including a semiconductor device is also provided.

公开(公告)号：US20170062431A1

公开(公告)日：2017-03-02

申请号：US15245671

申请日：2016-08-24

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Geert Van der Plas ,  Mirko Scholz

IPC: H01L27/092 ,  H01L21/266 ,  H01L27/06 ,  H01L21/033 ,  H01L29/808 ,  H01L29/66

CPC classification number: H01L27/0928 ,  H01L21/0332 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/098 ,  H01L29/1058 ,  H01L29/456 ,  H01L29/66128 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8611

Abstract: The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

Abstract translation: 所公开的技术涉及半导体，更具体地涉及结型场效应晶体管（JFET）。 一方面，一种制造JFET的方法包括在衬底中形成第一掺杂剂阱，其中阱通过第二掺杂剂类型的隔离区与衬底隔离。 该方法另外包括在阱的表面处注入第二掺杂剂类型的掺杂剂以形成JFET的源极，漏极和沟道，以及在阱的表面处注入第一掺杂剂类型的掺杂剂，以形成 JFET栅极。 该方法还包括在植入第一类型的掺杂剂和第二类型的掺杂剂之前，在阱上形成预金属电介质（PMD）层并在源上形成PMD层中的接触开口，漏极和 大门。 PMD层的厚度使得通过PMD层注入第一类掺杂剂和第二类掺杂剂形成沟道。 该方法还包括在注入第一类型的掺杂剂和第二类型的掺杂剂之后，将源极，漏极和栅极硅化，并在接触开口中形成金属接触。