公开(公告)号：US20240371874A1

公开(公告)日：2024-11-07

申请号：US18688594

申请日：2021-09-03

Applicant: IMEC VZW ,  HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Amita Rawat ,  Hao Wu ,  Geert Hellings ,  Krishna Kumar Bhuwalka

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A nanostructure according to the present disclosure comprises a pair of nanosheet or nanowire transistors configured to conduct charge by carriers of opposite polarity (such as n and p type carriers), wherein one of the pair of transistors is provided with inner spacers and the other is not provided with inner spacers. Depending on the type of charge carrier, the omission of the inner spacers may improve the admittance of the device. This is demonstrated in an example embodiment comprising a Si-channel PMOS nanosheet transistor. Conversely, in a Si-channel NMOS nanosheet transistor, the omission of the inner spacers has a negative effect on the parasitic capacitance that outweighs some of the benefits of the inner spacer omission. An example embodiment of the present disclosure includes complementary NMOS and PMOS silicon transistors, wherein the NMOS is provided with inner spacers and the PMOS is not provided with inner spacers.

公开(公告)号：US20230178629A1

公开(公告)日：2023-06-08

申请号：US18060945

申请日：2022-12-01

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Geert Hellings ,  Bilal Chehab ,  Julien Ryckaert ,  Naoto Horiguchi

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

CPC classification number: H01L29/66439 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545

Abstract: A method is provided for forming a FET device. The method includes: forming a preliminary device structure comprising a fin structure comprising a layer stack comprising channel layers and non-channel layers alternating the channel layers, and a deposited layer along a first side of the fin structure and a dummy structure along a second side of the fin structure; forming a mask line; forming along a first side of the fin structure a source and drain trench in the deposited layer; forming a set of source and drain cavities in the layer stack, by etching the fin structure from the source trench and the drain trench; forming a source body and a drain body comprising a respective common body portion a set of prongs protruding from the respective common body portion into the source and drain cavities; embedding the mask line in a cover material and removing the mask structure; forming a gate trench by etching the dummy structure; forming a set of gate cavities in the layer stack by etching the fin structure from the gate trench; and forming a gate body comprising a common gate body portion in the gate trench and a set of gate prongs protruding from the common gate body portion into the gate cavities.

公开(公告)号：US20250157914A1

公开(公告)日：2025-05-15

申请号：US18946788

申请日：2024-11-13

Applicant: Imec vzw

Inventor： James Edward Myers ,  Geert Hellings

IPC: H01L23/50 ,  G06F1/10

Abstract: An integrated circuit device includes a clock distribution network that includes a clock mesh formed by first clock lines and second clock lines. The first clock lines and the second clock lines are arranged at the same level in a backside interconnect structure of the integrated circuit device and are interconnected by crossing each other.

公开(公告)号：US10469083B2

公开(公告)日：2019-11-05

申请号：US15644614

申请日：2017-07-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Erik Bury ,  Jacopo Franco ,  Geert Hellings ,  Robin Degraeve ,  Benjamin Kaczer

IPC: H03K19/003 ,  H01L21/326 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H04L9/14 ,  H01L23/00 ,  H04L9/08 ,  H04L9/32 ,  G09C1/00 ,  H03K17/00

Abstract: A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.

公开(公告)号：US20170062431A1

公开(公告)日：2017-03-02

申请号：US15245671

申请日：2016-08-24

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Geert Van der Plas ,  Mirko Scholz

IPC: H01L27/092 ,  H01L21/266 ,  H01L27/06 ,  H01L21/033 ,  H01L29/808 ,  H01L29/66

CPC classification number: H01L27/0928 ,  H01L21/0332 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/098 ,  H01L29/1058 ,  H01L29/456 ,  H01L29/66128 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8611

Abstract: The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

Abstract translation: 所公开的技术涉及半导体，更具体地涉及结型场效应晶体管（JFET）。 一方面，一种制造JFET的方法包括在衬底中形成第一掺杂剂阱，其中阱通过第二掺杂剂类型的隔离区与衬底隔离。 该方法另外包括在阱的表面处注入第二掺杂剂类型的掺杂剂以形成JFET的源极，漏极和沟道，以及在阱的表面处注入第一掺杂剂类型的掺杂剂，以形成 JFET栅极。 该方法还包括在植入第一类型的掺杂剂和第二类型的掺杂剂之前，在阱上形成预金属电介质（PMD）层并在源上形成PMD层中的接触开口，漏极和 大门。 PMD层的厚度使得通过PMD层注入第一类掺杂剂和第二类掺杂剂形成沟道。 该方法还包括在注入第一类型的掺杂剂和第二类型的掺杂剂之后，将源极，漏极和栅极硅化，并在接触开口中形成金属接触。

公开(公告)号：US20230025767A1

公开(公告)日：2023-01-26

申请号：US17869289

申请日：2022-07-20

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Hellings ,  Geert Van der Plas

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/786

Abstract: An example includes a semiconductor structure including a semiconductor layer, front-side logic devices arranged in a front-side of the semiconductor layer, four epitaxial layers on a back-side of the semiconductor layer, where the four epitaxial layers include a first epitaxial layer of a first conductivity type, a second epitaxial layer of a second conductivity type, a third epitaxial layer of the second conductivity type, and a fourth epitaxial layer of the first conductivity type, a plurality of back-side contacts exposed at a back-side surface of the fourth epitaxial layer, where the plurality of back-side contacts include a set of first terminal contacts extending into and contacting the fourth epitaxial layer, a set of second terminal contacts extending into and contacting the second epitaxial layer, a set of first gate contacts extending into the third epitaxial layer, and a set of second gate contacts extending into the first epitaxial layer.

公开(公告)号：US20210159321A1

公开(公告)日：2021-05-27

申请号：US17099339

申请日：2020-11-16

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R & D

Inventor： Koen Martens ,  Sybren Santermans ,  Geert Hellings ,  David Barge

IPC: H01L29/66 ,  G01N27/414

Abstract: A method for forming a sensor is provided. The method includes: providing an active region comprising a channel having: a length, and a periphery consisting of one or more surfaces having said length, said periphery comprising a first part and a second part, each part having said length, the first part representing from 10 to 75% of the area of the periphery and the second part representing from 25 to 90% of the area of the periphery; providing a first dielectric structure on the entire first part, the first dielectric structure having a maximal equivalent oxide thickness; and providing a second dielectric structure on the entire second part, the second dielectric structure having a minimal equivalent oxide thickness larger than the maximal equivalent oxide thickness of the first dielectric structure.

公开(公告)号：US10566434B2

公开(公告)日：2020-02-18

申请号：US15853136

申请日：2017-12-22

Applicant: IMEC VZW

Inventor： Geert Hellings

IPC: H01L29/423 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/321

Abstract: The disclosed technology generally relates to semiconductor structures and methods of forming the semiconductor structures, and more particularly to semiconductor structures related to a gate-all-around field effect transistor and a fin field effect transistor. In one aspect, a method of forming field effect transistors includes forming in a first region of a substrate a first semiconductor feature and forming in a second region of the substrate a second semiconductor feature. Each of the first and second semiconductor features comprises a fin-shaped semiconductor feature including a vertical stack of at least a first semiconductor material layer and a second semiconductor material layer formed over the first semiconductor material layer. The method additionally includes selectively etching to remove the first semiconductor material layer along a longitudinal section of the first semiconductor feature to form a suspended longitudinal first semiconductor feature of a remaining second semiconductor material layer, while masking the second region to prevent etching of the second semiconductor feature. The method additionally includes forming a gate-all-around electrode surrounding the suspended longitudinal first semiconductor feature in the first region. The method further includes forming a gate electrode on the fin-shaped second semiconductor feature in the second region.

公开(公告)号：US09391060B2

公开(公告)日：2016-07-12

申请号：US14581008

申请日：2014-12-23

Applicant: IMEC vzw

Inventor： Geert Hellings ,  Dimitri Linten

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0248 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/7851

Abstract: An electrostatic discharge (ESD) protection device implemented in finFET technology is disclosed. The device has a reduced thickness shallow trench isolation (STI) layer which allows migration of high-doped drain implants therethrough to form regions extending under the STI layer thereby creating a planar-like region under the STI layer. Further, the regions are formed in an n-well layer provided between a substrate and the STI layer. The formation of the planar-like region under the STI layer has the advantage that part of the thermal energy produced in the device during an ESD event is generated under the STI layer where it can be more efficiently dissipated towards a substrate.

Abstract translation: 公开了一种以finFET技术实现的静电放电（ESD）保护器件。 器件具有减小厚度的浅沟槽隔离（STI）层，其允许高掺杂漏极注入通过其迁移以形成在STI层下延伸的区域，从而在STI层下面形成平面状区域。 此外，这些区域形成在设置在基板和STI层之间的n阱层中。 STI层下方的平面状区域的形成具有以下优点：在ESD事件期间在器件中产生的热能的一部分在STI层下产生，其中可以更有效地朝向衬底散发。

公开(公告)号：US20240429274A1

公开(公告)日：2024-12-26

申请号：US18753824

申请日：2024-06-25

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Pieter Schuddinck

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Provided herein is a nanosheet device that includes a first and a second transistor structure, each comprising a respective source region, drain region, and channel region extending between the respective source and drain regions, a dielectric wall, a gate structure, and a gate spacer, wherein the channel region of the first transistor structure includes a first set of vertically stacked channel layers, wherein each channel layer of the first set of vertically stacked channel layers has an inward facing surface contacting a first side surface of the dielectric wall, and wherein the channel region of the second transistor structure includes a second set of vertically stacked channel layers, and wherein each channel layer of the second set of vertically stacked channel layers has an inward facing surface contacting a second side surface, opposite to the first side surface, of the dielectric wall