公开(公告)号：US20200212199A1

公开(公告)日：2020-07-02

申请号：US16723742

申请日：2019-12-20

Applicant: IMEC VZW

Inventor： Shih-Hung Chen ,  Dimitri Linten

IPC: H01L29/66 ,  H01L27/088 ,  H01L27/02 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device and a method for forming such are provided, the device including: a substrate, a plurality of parallel active semiconductor patterns that extend through a drain-side region and a source-side region, a metal drain contact in the drain-side region, an active gate pattern, a first dummy gate pattern, and a second dummy gate pattern that all extend across the active semiconductor patterns, and a metal interconnect structure located in a region between the first and the second dummy gate patterns. The active semiconductor patterns are doped with a dopant in portions exposed by the dummy gates in dummy gate regions that include the gate cut regions of the first and second dummy gate patterns. The metal interconnect structure connects each of a second subset of the active semiconductor patterns to a respective at least one of a first subset of the active semiconductor patterns.

公开(公告)号：US09391060B2

公开(公告)日：2016-07-12

申请号：US14581008

申请日：2014-12-23

Applicant: IMEC vzw

Inventor： Geert Hellings ,  Dimitri Linten

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0248 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/7851

Abstract: An electrostatic discharge (ESD) protection device implemented in finFET technology is disclosed. The device has a reduced thickness shallow trench isolation (STI) layer which allows migration of high-doped drain implants therethrough to form regions extending under the STI layer thereby creating a planar-like region under the STI layer. Further, the regions are formed in an n-well layer provided between a substrate and the STI layer. The formation of the planar-like region under the STI layer has the advantage that part of the thermal energy produced in the device during an ESD event is generated under the STI layer where it can be more efficiently dissipated towards a substrate.

Abstract translation: 公开了一种以finFET技术实现的静电放电（ESD）保护器件。 器件具有减小厚度的浅沟槽隔离（STI）层，其允许高掺杂漏极注入通过其迁移以形成在STI层下延伸的区域，从而在STI层下面形成平面状区域。 此外，这些区域形成在设置在基板和STI层之间的n阱层中。 STI层下方的平面状区域的形成具有以下优点：在ESD事件期间在器件中产生的热能的一部分在STI层下产生，其中可以更有效地朝向衬底散发。

公开(公告)号：US11362195B2

公开(公告)日：2022-06-14

申请号：US16723742

申请日：2019-12-20

Applicant: IMEC VZW

Inventor： Shih-Hung Chen ,  Dimitri Linten

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088

Abstract: A semiconductor device and a method for forming such are provided, the device including: a substrate, a plurality of parallel active semiconductor patterns that extend through a drain-side region and a source-side region, a metal drain contact in the drain-side region, an active gate pattern, a first dummy gate pattern, and a second dummy gate pattern that all extend across the active semiconductor patterns, and a metal interconnect structure located in a region between the first and the second dummy gate patterns. The active semiconductor patterns are doped with a dopant in portions exposed by the dummy gates in dummy gate regions that include the gate cut regions of the first and second dummy gate patterns. The metal interconnect structure connects each of a second subset of the active semiconductor patterns to a respective at least one of a first subset of the active semiconductor patterns.

公开(公告)号：US09087849B2

公开(公告)日：2015-07-21

申请号：US14478817

申请日：2014-09-05

Applicant: IMEC VZW

Inventor： Shih-Hung Chen ,  Dimitri Linten

IPC: H01L27/02 ,  H01L23/00 ,  H01L29/78

CPC classification number: H01L23/564 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosed technology generally relates to electrostatic discharge protection devices that protect circuits from transient electrical events and more particularly to low-voltage triggered silicon-controlled rectifier devices implemented using a bulk fin field-effect transistor technology. In one aspect, an electrostatic discharge protection device comprises a low-voltage triggered silicon-controlled rectifier having an embedded grounded-gate n-channel metal oxide semiconductor structure implemented as a bulk fin field-effect transistor having a plurality of fin structures. The fin structures direct current from an avalanche zone to a gate formed over the fin structure. The electrostatic discharge protection device has a higher trigger current and a lower leakage current than a similar device having a planar embedded grounded-gate n-channel metal oxide semiconductor structure because the current flow is restricted by the fin structures.

Abstract translation: 所公开的技术通常涉及保护电路免受瞬态电事件的静电放电保护装置，更具体地涉及使用体翅片场效应晶体管技术实现的低电压触发的可控硅整流器件。 一方面，静电放电保护装置包括具有嵌入的接地栅极n沟道金属氧化物半导体结构的低电压触发的可控硅整流器，其被实现为具有多个鳍结构的体翅片场效应晶体管。 翅片结构将电流从雪崩区域引导到形成在鳍结构上的栅极。 与具有平面嵌入式接地栅极n沟道金属氧化物半导体结构的类似器件相比，静电放电保护器具有较高的触发电流和较低的漏电流，因为电流被翅片结构限制。

公开(公告)号：US11114435B2

公开(公告)日：2021-09-07

申请号：US15382376

申请日：2016-12-16

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Geert Hellings ,  Roman Boschke ,  Dimitri Linten ,  Naoto Horiguchi

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.

公开(公告)号：US10680098B2

公开(公告)日：2020-06-09

申请号：US15389217

申请日：2016-12-22

Applicant: IMEC VZW

Inventor： Shih-Hung Chen ,  Dimitri Linten ,  Geert Hellings

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08

Abstract: An LDMOS device in FinFET technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. The device further includes a first fin in the first region, extending into the second region, the first fin including a doped source region connected with a first local interconnect. The device further includes a second fin in the second region, including a doped drain region connected with a second local interconnect. The device further includes a third fin parallel with the first and second fins including a doped drain region connected with the second local interconnect. The device further includes a gate over the first fin at the border between the first and second regions. A first current path runs over the first and second fins. A second current path runs over and perpendicular to the first fin towards the third fin.

公开(公告)号：US20170194487A1

公开(公告)日：2017-07-06

申请号：US15389217

申请日：2016-12-22

Applicant: IMEC VZW

Inventor： Shih-Hung Chen ,  Dimitri Linten ,  Geert Hellings

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41791 ,  H01L29/7835 ,  H01L29/7851

Abstract: An LDMOS device in FinFET technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. The device further includes a first fin in the first region, extending into the second region, the first fin including a doped source region connected with a first local interconnect. The device further includes a second fin in the second region, including a doped drain region connected with a second local interconnect. The device further includes a third fin parallel with the first and second fins including a doped drain region connected with the second local interconnect. The device further includes a gate over the first fin at the border between the first and second regions. A first current path runs over the first and second fins. A second current path runs over and perpendicular to the first fin towards the third fin.