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公开(公告)号：DE10312261B4
公开(公告)日：2005-09-29
申请号：DE10312261
申请日：2003-03-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ALEXANDER GEORG W , LEE JINHWAN
Abstract: A delay lock loop circuit includes a variable voltage regulator and a forward delay circuit. The variable voltage regulator receives an external supply voltage and issues a variable supply voltage. The forward delay circuit is powered by the variable supply voltage.
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公开(公告)号：DE10312261A1
公开(公告)日：2003-10-09
申请号：DE10312261
申请日：2003-03-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ALEXANDER GEORG W , LEE JINHWAN
Abstract: A delay lock loop circuit includes a variable voltage regulator and a forward delay circuit. The variable voltage regulator receives an external supply voltage and issues a variable supply voltage. The forward delay circuit is powered by the variable supply voltage.
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公开(公告)号：DE10312260A1
公开(公告)日：2003-10-09
申请号：DE10312260
申请日：2003-03-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ALEXANDER GEORG W , PARTSCH TORSTEN
Abstract: A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a first delayed clock signal. The forward delay circuit adjustably shifts in time the first delayed clock signal relative to the reference clock signal. A fixed delay circuit receives the first delayed clock signal and issues a second delayed clock signal. A feedback delay circuit receives a selected one of the first delayed and the second delayed clock signals, and issues a feedback clock signal. The feedback clock signal is shifted in time relative to the selected one of the first delayed and the second delayed clock signals.
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