公开(公告)号：DE10335096A1

公开(公告)日：2004-02-12

申请号：DE10335096

申请日：2003-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAKER STEVEN M ,  BERRY II JON S ,  COUSINEAU BRAIN ,  GERSTMEIER GUENTER ,  HEGDE MALATI ,  LEE JINHWAN ,  MALDEI MICHAEL

IPC: H01L21/318 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/148 ,  H01L29/76

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

公开(公告)号：DE10312261A1

公开(公告)日：2003-10-09

申请号：DE10312261

申请日：2003-03-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ALEXANDER GEORG W ,  LEE JINHWAN

IPC: H03L7/081 ,  H03L7/06 ,  H03K5/135

Abstract: A delay lock loop circuit includes a variable voltage regulator and a forward delay circuit. The variable voltage regulator receives an external supply voltage and issues a variable supply voltage. The forward delay circuit is powered by the variable supply voltage.

公开(公告)号：DE10312261B4

公开(公告)日：2005-09-29

申请号：DE10312261

申请日：2003-03-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ALEXANDER GEORG W ,  LEE JINHWAN

IPC: H03L7/081 ,  H03L7/06 ,  H03K5/135

Abstract: A delay lock loop circuit includes a variable voltage regulator and a forward delay circuit. The variable voltage regulator receives an external supply voltage and issues a variable supply voltage. The forward delay circuit is powered by the variable supply voltage.

公开(公告)号：DE102004009626A1

公开(公告)日：2004-11-25

申请号：DE102004009626

申请日：2004-02-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAKER STEVEN M ,  BERRY II JON S ,  COUSINEAU BRAIN ,  GERSTMEIER GUENTER ,  HEDGE MALATI ,  LEE JINHWAN ,  MALDEI MICHAEL ,  ZHANG WENCHAO

IPC: H01L21/02 ,  H01L27/08 ,  H01L29/94 ,  H01L29/768 ,  H01L21/8234

Abstract: A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation layer is formed over the semiconductor substrate. Gate electrodes are formed on top of the insulation layer. An array of CD contact pads including a plurality of CD contacts are connected to the semiconductor substrate in a first predetermined number of locations. An array of CG contact pads including at least one CG contact connected to the gate electrodes such that each CG contact is connected to a respective gate electrode above a respective insulation island in a second predetermined number of locations.

公开(公告)号：DE10347428A1

公开(公告)日：2004-05-27

申请号：DE10347428

申请日：2003-10-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MALDEI MICHAEL ,  GERSTMEIER GUENTER ,  BAKER STEVEN M ,  BERRY II JON S ,  LEE JINHWAN ,  COUSINEAU BRIAN

IPC: H01L21/336 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/10 ,  H01L29/40 ,  H01L29/739 ,  H01L29/76 ,  H01L29/78

Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.