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    INTERRUPT AND TRAP HANDLING IN AN EMBEDDED MULTI-THREADED PROCESSOR TO AVOID PRIORITY INVERSION AND MAINTAIN REAL-TIME OPERATION
    2.
    发明申请
    INTERRUPT AND TRAP HANDLING IN AN EMBEDDED MULTI-THREADED PROCESSOR TO AVOID PRIORITY INVERSION AND MAINTAIN REAL-TIME OPERATION 审中-公开
    嵌入式多线程处理器的中断和跟踪处理避免了优先级反转和维护实时操作

    公开(公告)号：WO2005050435A3

    公开(公告)日：2006-04-27

    申请号：PCT/EP2004012713

    申请日：2004-11-10

    Applicant: INFINEON TECHNOLOGIES AG ,  ARNOLD ROGER ,  MARTIN DANIEL ,  NORDEN ERIK ,  OBER ROBERT E

    Inventor： ARNOLD ROGER ,  MARTIN DANIEL ,  NORDEN ERIK ,  OBER ROBERT E

    IPC: G06F9/46 ,  G06F9/48 ,  G06F13/26

    CPC classification number: G06F9/4812 ,  G06F9/462 ,  G06F13/26

    Abstract: A real-time, multi-threaded embedded system includes rules for handling traps and interrupts to avoid problems such as priority inversion and re-entrancy. By defining a global interrupt priority value for all active threads and only accepting interrupts having a priority higher than the global interrupt priority value, priority inversion can be avoided. Switching to the same thread before any interrupt servicing, and disabling interrupts and thread switching during interrupt servicing can simplify the interrupt handling logic. By storing trap background data for traps and servicing traps only in their originating threads, trap traceability can be preserved. By disabling interrupts and thread switching during trap servicing, unintended trap re-entrancy and servicing disruption can be prevented.

    Abstract translation: 一个实时的多线程嵌入式系统包括处理陷阱和中断的规则，以避免诸如优先级倒置和重入的问题。 通过为所有活动线程定义全局中断优先级值，并且仅接受优先级高于全局中断优先级值的中断，可以避免优先级反转。 在任何中断服务之前切换到同一个线程，并且在中断服务期间禁用中断和线程切换可以简化中断处理逻辑。 通过仅在其始发线程中存储陷阱和维护陷阱的陷阱后台数据，可以保留陷阱跟踪性。 通过在陷阱维护期间禁用中断和线程切换，可以防止意外的陷阱重入和服务中断。

    3.
    发明专利
    未知

    公开(公告)号：DE602005018696D1

    公开(公告)日：2010-02-25

    申请号：DE602005018696

    申请日：2005-02-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ARNOLD ROGER ,  MARTIN DANIEL ,  NORDEN ERIK ,  OBER ROBERT E

    IPC: G06F9/38 ,  G06F9/44 ,  G06F9/46 ,  G06F9/48

    Abstract: A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.

    4.
    发明专利
    未知

    公开(公告)号：DE602005005726T2

    公开(公告)日：2009-04-30

    申请号：DE602005005726

    申请日：2005-02-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ARNOLD ROGER ,  MARTIN DANIEL ,  NORDEN ERIK ,  OBER ROBERT E

    IPC: G06F9/38 ,  G06F9/46 ,  G06F9/48

    Abstract: A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.

    5.
    发明专利
    未知

    公开(公告)号：DE102004013676B4

    公开(公告)日：2007-06-21

    申请号：DE102004013676

    申请日：2004-03-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： AHMAD SAGHEER ,  ARNOLD ROGER ,  KNOTH MATTHIAS

    IPC: G06F9/32 ,  G06F9/44

    Abstract: A loop instruction, at least one target instruction, and an associated trigger address are cached during loop entry. During each loop iteration, the processor predicts whether the loop will be taken or not-taken in a subsequent iteration. When pre-fetch of the cached loop instruction is subsequently detected (i.e., by comparing the trigger address with the current program counter value), the loop taken/not-taken prediction is used to fetch either loop body instructions (when predicted taken) or fall-through instructions (when predicted not-taken). The cached loop instruction is then executed and the loop taken/not-taken prediction is verified using a dedicated loop execution circuit while a penultimate loop body instruction is executed in the processor execution stage (pipeline). When a previous loop taken prediction is verified, the cached target instruction is executed, and then the fetched loop body instructions are executed. When a loop not-taken prediction is verified, the fetched fall-through instructions are executed.

    7.
    发明专利
    未知

    公开(公告)号：DE602005005726D1

    公开(公告)日：2008-05-15

    申请号：DE602005005726

    申请日：2005-02-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ARNOLD ROGER ,  MARTIN DANIEL ,  NORDEN ERIK ,  OBER ROBERT E

    IPC: G06F9/38 ,  G06F9/46 ,  G06F9/48

    Abstract: A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.

    8.
    发明专利
    未知

    公开(公告)号：DE102004013676A1

    公开(公告)日：2004-12-23

    申请号：DE102004013676

    申请日：2004-03-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： AHMAD SAGHEER ,  ARNOLD ROGER ,  KNOTH MATTHIAS

    IPC: G06F9/32 ,  G06F9/44

    Abstract: A loop instruction, at least one target instruction, and an associated trigger address are cached during loop entry. During each loop iteration, the processor predicts whether the loop will be taken or not-taken in a subsequent iteration. When pre-fetch of the cached loop instruction is subsequently detected (i.e., by comparing the trigger address with the current program counter value), the loop taken/not-taken prediction is used to fetch either loop body instructions (when predicted taken) or fall-through instructions (when predicted not-taken). The cached loop instruction is then executed and the loop taken/not-taken prediction is verified using a dedicated loop execution circuit while a penultimate loop body instruction is executed in the processor execution stage (pipeline). When a previous loop taken prediction is verified, the cached target instruction is executed, and then the fetched loop body instructions are executed. When a loop not-taken prediction is verified, the fetched fall-through instructions are executed.

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