Abstract:
The invention relates to a digital circuit (1) comprising asynchronous circuitry (2), in which the input voltage of the asynchronous circuitry (2) is varied using a random voltage jitter. The random modification of the input voltage causes a temporal jitter in the processing of the individual operations within the asynchronous circuitry, thus preventing individual measurements from being synchronised with the circuitry during side-channel attacks.
Abstract:
The invention relates to a screening device comprising means for optical and/or electrical screening which are arranged in the semiconductor chip on the side of the integrated circuit facing the substrate. Preferred embodiments use an SOI substrate with the integrated circuit in the body silicon layer (3) and with the isolator layer (2) as an optical screening device of the bulk silicon layer (1). Electrical conductors (5) can be provided in the bulk silicon layer as an optical and electrical screening device and can be connected to the circuit by means of platings (4).
Abstract:
An IC chip having a protective structure that is distributed over the semiconductor chip in such a manner that it is not possible to trigger a malfunction in the circuit by means of irradiation without the protective structure also being affected by the irradiation. To this end, redundant conductors are provided or connections having radiation-dependent conductivity or dielectric constant are provided or the test lines of a memory are arranged between the bit lines.
Abstract:
The invention relates to a digital circuit (1) comprising asynchronous circuitry (2), in which the input voltage of the asynchronous circuitry (2) is varied using a random voltage jitter. The random modification of the input voltage causes a temporal jitter in the processing of the individual operations within the asynchronous circuitry, thus preventing individual measurements from being synchronised with the circuitry during side-channel attacks.
Abstract:
A shielding device includes optical and/or electrical shielding disposed on the side of the integrated circuit in the semiconductor chip facing the substrate. Preferred configurations use an SOI substrate with the integrated circuit in the body silicon layer and the insulator layer as a device for optical shielding from the bulk silicon layer. Electrical conductors may be present as an optical and electrical shielding device in the bulk silicon layer, and they may be connected to the circuit using vias.
Abstract:
An IC chip having a protective structure that is distributed over the semiconductor chip in such a manner that it is not possible to trigger a malfunction in the circuit by means of irradiation without the protective structure also being affected by the irradiation. To this end, redundant conductors are provided or connections having radiation-dependent conductivity or dielectric constant are provided or the test lines of a memory are arranged between the bit lines.
Abstract:
An energy supply device having an intermediate energy store, a main energy store and a circuit device is provided. The circuit device contains at least two output states, whereby the intermediate energy store is connected to an energy supply input in a first output state and to the main energy store, which is connected to the energy supply output, in a second output state.
Abstract:
A shielding device includes optical and/or electrical shielding disposed on the side of the integrated circuit in the semiconductor chip facing the substrate. Preferred configurations use an SOI substrate with the integrated circuit in the body silicon layer and the insulator layer as a device for optical shielding from the bulk silicon layer. Electrical conductors may be present as an optical and electrical shielding device in the bulk silicon layer, and they may be connected to the circuit using vias.
Abstract:
In a digital circuit comprising an asynchronous circuit, the supply voltage of the asynchronous circuit is varied by means of a random voltage jitter. The random variation of the supply voltage causes a time jitter in the processing of the individual operations within the asynchronous circuit, whereby an artificial synchronizing of individual measurements in side channel attacks is prevented.