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    CHIPCARD CIRCUIT WITH MONITORED ACCESS TO THE TEST MODE
    4.
    发明申请
    CHIPCARD CIRCUIT WITH MONITORED ACCESS TO THE TEST MODE 审中-公开
    SMART CARD电路监控进入到测试模式

    公开(公告)号：WO0154056A3

    公开(公告)日：2001-12-06

    申请号：PCT/DE0100141

    申请日：2001-01-15

    Applicant: INFINEON TECHNOLOGIES AG ,  WALLSTAB STEFAN

    Inventor： WALLSTAB STEFAN

    IPC: G01R31/317 ,  G06K19/073

    CPC classification number: G01R31/31701

    Abstract: The invention relates to a circuit for monitoring the access to the test mode of a chip circuit, comprising a fusible bridge (1), which can be fired by a firing transistor (2). A flip-flop (9), which permits the access to the test mode, can be set, due to the voltage drop thus created, with the aid of a flank detector (6). The number of times the test mode is accessed can be determined from the number of expended fusible bridges (1).

    Abstract translation: 一种用于监测进入该测试模式电路，一个芯片电路包括一个雷管电桥（1），经击发晶体管（2）能够被点燃。 由电压降，其特征在于所产生的触发器（9）由边缘检测器（6），其提供进入测试模式的装置设定。 条目上的点火熔断（1）的数目的数目可在测试模式下进行检测。

    6.
    发明专利
    未知

    公开(公告)号：DE10128573A1

    公开(公告)日：2003-01-02

    申请号：DE10128573

    申请日：2001-06-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ECKSTEIN GERNOT ,  AUMUELLER CHRISTIAN ,  WALLSTAB STEFAN

    IPC: G06F1/00 ,  G06F21/75 ,  G06F21/76 ,  H04L9/10 ,  H04L9/00 ,  G06F1/26

    Abstract: The invention relates to a digital circuit (1) comprising asynchronous circuitry (2), in which the input voltage of the asynchronous circuitry (2) is varied using a random voltage jitter. The random modification of the input voltage causes a temporal jitter in the processing of the individual operations within the asynchronous circuitry, thus preventing individual measurements from being synchronised with the circuitry during side-channel attacks.

    7.
    发明专利
    未知

    公开(公告)号：AT293796T

    公开(公告)日：2005-05-15

    申请号：AT00100952

    申请日：2000-01-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WALLSTAB STEFAN

    IPC: G01R31/317 ,  G06K19/073

    Abstract: The circuit has at least one once-only switchable circuit element (1) whose switching state determines accessibility to a test mode. The circuit element may consist of a fusible bridge connected in series with an ignition transistor. A sense transistor may be connected in parallel with the ignition transistor to form a voltage divider, which is connected to an edge detector, such as a bi-stable flip-flop.

    9.
    发明专利
    未知

    公开(公告)号：DE10105987A1

    公开(公告)日：2002-08-29

    申请号：DE10105987

    申请日：2001-02-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： OTTERSTEDT JAN ,  WALLSTAB STEFAN ,  HORVAT HELMUT

    IPC: G06F15/78 ,  G06F21/32 ,  G06F21/72 ,  G06F21/77 ,  G06K19/073 ,  H04N5/00 ,  G06F12/14

    Abstract: The invention relates to a data processing device comprising a functional programmable logic circuit having a programming interface. The invention is characterized in that it is provided with an authorization control unit protecting the programming interface from unauthorized access. This makes it possible to carry out customer-specific functional adaptation of the semiconductor blocks and to prevent a subsequent change by unauthorized parties.

    10.
    发明专利
    未知

    公开(公告)号：DE50212509D1

    公开(公告)日：2008-08-28

    申请号：DE50212509

    申请日：2002-01-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HORVAT HELMUT ,  OTTERSTEDT JAN ,  WALLSTAB STEFAN

    IPC: G06F15/78 ,  G06F21/32 ,  G06F21/72 ,  G06F21/77 ,  G06K19/073 ,  H04N5/00

    Abstract: The invention relates to a data processing device with a functionally programmable logic circuit and a programming interface. An authorization control unit is provided, which protects the programming interface against an unauthorized access. This enables the functions of a semiconductor module to be changed in a customer-specific manner while preventing unauthorized entities from subsequently changing the functionality.

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