公开(公告)号：AU2003224151A1

公开(公告)日：2003-11-11

申请号：AU2003224151

申请日：2003-05-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOCK HOLGER

IPC: G06F7/38

公开(公告)号：DE602004005959D1

公开(公告)日：2007-05-31

申请号：DE602004005959

申请日：2004-02-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUZZI RAIMONDO ,  BUCCI MARCO ,  BOCK HOLGER ,  DREXEL WERNER

IPC: H03K3/84 ,  G06F7/58

Abstract: An apparatus for providing a random bit stream comprises a first means (302) for providing a clock signal (310), a second means (306) for providing a sample signal (314), a third means (322) for activating the first and second means (302, 306) such that a sampling edge of the sample signal (314) is aligned to an edge of the clock signal. The apparatus further comprises a forth means (308) for sampling the clock signal (310) responsive to the sampling edge of the sample signal (314) and for generating a random bit (316) dependent on the sampling result. Further, the apparatus comprises a fifth means (328) for deactivating the first and second means (302, 306). Successive random bits (316) form a random bit stream.

公开(公告)号：DE102005044333A1

公开(公告)日：2007-03-29

申请号：DE102005044333

申请日：2005-09-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOCK HOLGER ,  KOWALCZYK GREGOR ,  HAID JOSEF

IPC: H03K3/037

Abstract: Master-slave flip flop including a master latch having a data input for receiving a data input signal, an inverting clock input for receiving a first clock signal, and a data output, a slave latch having a data input which is connected to the data output of the master latch, a clock input for receiving a second clock signal, and a data output for outputting an output signal, and a time delay element connects the clock input of the slave latch to the clock input of the master latch.

公开(公告)号：DE10227618B4

公开(公告)日：2007-02-01

申请号：DE10227618

申请日：2002-06-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOCK HOLGER

IPC: H03K19/00 ,  H03K5/151 ,  H03K19/003

Abstract: A logic circuit includes an input for one or several input operands, an output for a result and an inverted result, a first circuit branch with a first logic assembly, which is coupled to the input and the output, to calculate the result, as well as a second circuit branch with a second logic assembly, which is coupled to the input and the output, to calculate the inverted result, wherein the first logic assembly and the second logic assembly have different run times for calculating the result and the inverted result, respectively. Further, a delay circuit and a compensation circuit, respectively, are provided in the first and/or second circuit branch to reduce a difference of the run times and the power consumptions, respectively, of the first and the second circuit branch.

公开(公告)号：DE502004003397D1

公开(公告)日：2007-05-16

申请号：DE502004003397

申请日：2004-01-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AIGNER MANFRED ,  BOCK HOLGER

IPC: H04L9/06

Abstract: In a device for calculating encrypted data from plaintext data or plaintext data from encrypted data, in which a cryptographic algorithm having an initial stage, an intermediate stage or final stage and an intermediate stage upstream of the final stage is implemented, the processor for performing the cryptographic algorithm is formed such that it performs either the initial stage or the final stage or both the initial stage and the final stage in a manner protected against a cryptographic attack, whereas the intermediate stage is performed in a manner unprotected against a cryptographic attack.

公开(公告)号：DE10303723A1

公开(公告)日：2004-08-19

申请号：DE10303723

申请日：2003-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOCK HOLGER ,  AIGNER MANFRED

IPC: H04L9/06 ,  G06F12/14

Abstract: In a device for calculating encrypted data from plaintext data or plaintext data from encrypted data, in which a cryptographic algorithm having an initial stage, an intermediate stage or final stage and an intermediate stage upstream of the final stage is implemented, the processor for performing the cryptographic algorithm is formed such that it performs either the initial stage or the final stage or both the initial stage and the final stage in a manner protected against a cryptographic attack, whereas the intermediate stage is performed in a manner unprotected against a cryptographic attack.

公开(公告)号：AU2003238502A1

公开(公告)日：2004-01-06

申请号：AU2003238502

申请日：2003-06-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOCK HOLGER

IPC: H03K5/151 ,  H03K19/003 ,  H03K19/00

Abstract: A logic circuit includes an input for one or several input operands, an output for a result and an inverted result, a first circuit branch with a first logic assembly, which is coupled to the input and the output, to calculate the result, as well as a second circuit branch with a second logic assembly, which is coupled to the input and the output, to calculate the inverted result, wherein the first logic assembly and the second logic assembly have different run times for calculating the result and the inverted result, respectively. Further, a delay circuit and a compensation circuit, respectively, are provided in the first and/or second circuit branch to reduce a difference of the run times and the power consumptions, respectively, of the first and the second circuit branch.

公开(公告)号：DE10223175A1

公开(公告)日：2003-12-11

申请号：DE10223175

申请日：2002-05-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RIEGEBAUER JOSEF ,  BEIT-GROGGER ANDREA ,  BOCK HOLGER

IPC: H04L9/06 ,  H04L9/14 ,  H04L9/28

Abstract: A method for data encryption in an integrated circuit arrangement has part procedural steps for protecting against unsanctioned analysis. A further, at least similar 'hidden' procedural step with a random selected key is carried out at least partly in parallel to a partial procedural step protecting against analysis. The randomly selected key is specifically a part-key. An Independent claim is given for a device for carrying out an data encoding procedure.

公开(公告)号：DE602004005959T2

公开(公告)日：2007-12-20

申请号：DE602004005959

申请日：2004-02-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUZZI RAIMONDO ,  BUCCI MARCO ,  BOCK HOLGER ,  DREXEL WERNER

IPC: H03K3/84 ,  G06F7/58

Abstract: An apparatus for providing a random bit stream comprises a first means (302) for providing a clock signal (310), a second means (306) for providing a sample signal (314), a third means (322) for activating the first and second means (302, 306) such that a sampling edge of the sample signal (314) is aligned to an edge of the clock signal. The apparatus further comprises a forth means (308) for sampling the clock signal (310) responsive to the sampling edge of the sample signal (314) and for generating a random bit (316) dependent on the sampling result. Further, the apparatus comprises a fifth means (328) for deactivating the first and second means (302, 306). Successive random bits (316) form a random bit stream.

公开(公告)号：DE102004062825B4

公开(公告)日：2006-11-23

申请号：DE102004062825

申请日：2004-12-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GAMMEL BERNDT ,  GOESSEL MICHAEL ,  BOCK HOLGER

IPC: H04L9/06

Abstract: Unit has first processor (S) determining output signal (Y), based on AES algorithm, and first comparison signal (V). A second processor (S 1) determines second comparison signal (V') and release unit for delivering output signal. Release unit is designed to carry out defence against external attack on output signal, when there is preset relation of both comparison signals, while first comparison signal is determined in different manner with respective second comparing signal for easy fault recognition. Independent claims are included for ; (1) operating method of cryptographic unit; (2) computer program.