公开(公告)号：DE10142011B4

公开(公告)日：2005-12-29

申请号：DE10142011

申请日：2001-08-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHWARZ MICHAEL ,  SAMEC CHRISTIAN ,  DREXEL WERNER ,  ZWEIMUELLER GERHARD

IPC: G01R19/165 ,  G01R15/04 ,  G01R15/08 ,  G01R35/00

公开(公告)号：DE602004005959D1

公开(公告)日：2007-05-31

申请号：DE602004005959

申请日：2004-02-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUZZI RAIMONDO ,  BUCCI MARCO ,  BOCK HOLGER ,  DREXEL WERNER

IPC: H03K3/84 ,  G06F7/58

Abstract: An apparatus for providing a random bit stream comprises a first means (302) for providing a clock signal (310), a second means (306) for providing a sample signal (314), a third means (322) for activating the first and second means (302, 306) such that a sampling edge of the sample signal (314) is aligned to an edge of the clock signal. The apparatus further comprises a forth means (308) for sampling the clock signal (310) responsive to the sampling edge of the sample signal (314) and for generating a random bit (316) dependent on the sampling result. Further, the apparatus comprises a fifth means (328) for deactivating the first and second means (302, 306). Successive random bits (316) form a random bit stream.

公开(公告)号：DE102009019884A1

公开(公告)日：2010-04-01

申请号：DE102009019884

申请日：2009-05-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BUCHSBAUM MARTIN ,  DREXEL WERNER ,  LIEBL MARTIN ,  PONTESEGGER CHRISTIAN ,  RAGGAM PETER

IPC: H04B5/02 ,  G06K7/10 ,  G08C17/00

公开(公告)号：DE602004005959T2

公开(公告)日：2007-12-20

申请号：DE602004005959

申请日：2004-02-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUZZI RAIMONDO ,  BUCCI MARCO ,  BOCK HOLGER ,  DREXEL WERNER

IPC: H03K3/84 ,  G06F7/58

Abstract: An apparatus for providing a random bit stream comprises a first means (302) for providing a clock signal (310), a second means (306) for providing a sample signal (314), a third means (322) for activating the first and second means (302, 306) such that a sampling edge of the sample signal (314) is aligned to an edge of the clock signal. The apparatus further comprises a forth means (308) for sampling the clock signal (310) responsive to the sampling edge of the sample signal (314) and for generating a random bit (316) dependent on the sampling result. Further, the apparatus comprises a fifth means (328) for deactivating the first and second means (302, 306). Successive random bits (316) form a random bit stream.

公开(公告)号：DE10142011A1

公开(公告)日：2003-04-03

申请号：DE10142011

申请日：2001-08-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHWARZ MICHAEL ,  SAMEC CHRISTIAN ,  DREXEL WERNER ,  ZWEIMUELLER GERHARD

IPC: G01R19/165 ,  G01R15/04

Abstract: The invention relates to a voltage sensor for monitoring a supply voltage, which is applied to a supply potential connection, at an upper and lower limit value. The voltage sensor comprises the following components: a first comparison means that compares the supply voltage at the lower limit value to a first reference voltage value by means of evaluation and outputs a first signal when this lower limit value is fallen below of; a second comparison means which compares the supply voltage at the upper limit value with a second reference voltage by means of evaluation and outputs a second signal when this upper limit value is exceeded, and; a calibrating means that is coupled to the first and second comparison means and enables the first and second comparison means to be calibrated by increasing or decreasing the supply voltage to be evaluated. The invention provides that the calibration is carried out after the manufacture of each circuit arrangement. The configuration of the voltage sensor is stored in a non-volatile memory. The voltage sensor is reconfigured each time a circuit arrangement containing the inventive voltage sensor is activated.