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公开(公告)号：WO02082256A3
公开(公告)日：2002-12-19
申请号：PCT/DE0201257
申请日：2002-04-05
Applicant: INFINEON TECHNOLOGIES AG , BREDERLOW RALF
Inventor： BREDERLOW RALF
CPC classification number: G06F7/588
Abstract: The invention relates to a random number generator comprising a number of semi-conductor elements comprising, on average, one electrically active disrupt cell in the frequency band which is important for processing, in the crystalline structure thereof. A suitable transistor is selected by a charge/detector unit and the charge thereof or an alteration of the charge in the electrically active disrupt cell of the selected transistor is determined. A random number is formed from the detected charge or alteration of the charge by means of a random number conversion unit.
Abstract translation: 随机数生成器具有许多在其晶体结构中具有用于处理频带中的重要的平均电活性缺陷的半导体器件。 与占用检测单元，合适的晶体管被选择，并且其职业或占领在确定所选择的晶体管的电活性缺陷的变化。 用随机数转换单元，一个随机数被从所确定的职业或铸件的变化而形成。
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2.发明申请INTEGRATED CIRCUIT ARRANGEMENT COMPRISING CAPACITORS AND PREFERABLY PLANAR TRANSISTORS, AND PRODUCTION METHOD 审中-公开集成电路安排与电容器，优选，平面晶体管和制造方法
公开(公告)号：WO2004038802A3
公开(公告)日：2004-09-10
申请号：PCT/DE0303354
申请日：2003-10-10
Applicant: INFINEON TECHNOLOGIES AG , BREDERLOW RALF , HARTWICH JESSICA , PACHA CHRISTIAN , ROESNER WOLFGANG , SCHULZ THOMAS
Inventor： BREDERLOW RALF , HARTWICH JESSICA , PACHA CHRISTIAN , ROESNER WOLFGANG , SCHULZ THOMAS
IPC: H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12
CPC classification number: H01L27/1085 , H01L21/84 , H01L27/10805 , H01L27/1203
Abstract: Disclosed is an integrated circuit arrangement (140), among others, comprising a preferably planar transistor (142) and a capacitor (144). The lower electrode of the capacitor (144) is disposed within an SOl substrate along with a channel section of the transistor (142). The inventive circuit arrangement (140) is easy to produce and has excellent electronic properties.
Abstract translation: 尤其公开了包含优选平面晶体管（142）和电容器（144）的集成电路装置（140）。 电容器（144）的下电极与SOI衬底中的晶体管（142）的沟道区共同布置。 电路装置（140）容易制造并具有优异的电子特性。
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公开(公告)号：WO03006981A3
公开(公告)日：2003-08-07
申请号：PCT/DE0202526
申请日：2002-07-10
Applicant: INFINEON TECHNOLOGIES AG , BREDERLOW RALF , EVERSMANN BJOERN-OLIVER , KOREN IVO , PAULUS CHRISTIAN , THEWES ROLAND
Inventor： BREDERLOW RALF , EVERSMANN BJOERN-OLIVER , KOREN IVO , PAULUS CHRISTIAN , THEWES ROLAND
IPC: G01N27/414 , G01N27/416 , G01N33/483 , G01N37/00 , G11C27/02 , G01N33/487 , H03F3/45
CPC classification number: G11C27/024 , G01N27/4148 , G01N33/48728
Abstract: The invention relates to a measuring cell for receiving an electric potential of a sample. Said cell has a common substrate for a sensor, which converts a sample into an electric potential and for an amplifier circuit, which is connected to the sensor. The measuring field contains several measuring cells. The measuring cell can also be used to subject a sample to an electric potential, by applying an electric signal to the amplifier circuit.
Abstract translation: 建议用于接收样品的电势，包括用于传感器的共用基板用于在样品中的电位反应的测量单元，以及连接到所述传感器的放大器电路。 测量场包含几个测量单元。 测量单元也可以被用于通过将电信号施加到所述放大器电路施加到样品的电势。
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4.发明申请FORCE SENSOR COMPRISING ORGANIC FIELD EFFECT TRANSISTORS AND PRESSURE SENSOR, POSITION SENSOR AND FINGERPRINT SENSOR THAT ARE BASED ON SAID FORCE SENSOR 审中-公开WITH有机场效应晶体管的力传感器，其上压力传感器，位置传感器和指纹传感器基于
公开(公告)号：WO2005096348A3
公开(公告)日：2005-12-08
申请号：PCT/DE2005000559
申请日：2005-03-30
Applicant: INFINEON TECHNOLOGIES AG , KLAUK HAGEN , HALIK MARCUS , ZSCHIESCHANG UTE , SCHMID GUENTER , DARLINSKI GRZEGORZ , WASER RAINER , BREDERLOW RALF
Inventor： KLAUK HAGEN , HALIK MARCUS , ZSCHIESCHANG UTE , SCHMID GUENTER , DARLINSKI GRZEGORZ , WASER RAINER , BREDERLOW RALF
CPC classification number: G06K9/00053
Abstract: The invention relates to a force sensor based on an organic field effect transistor (10) that is applied to a substrate (1; 11). According to the invention, a mechanical force that acts on the transistor causes a corresponding modification of the source-drain voltage or the source-drain current (ID), whereby said modification can be respectively detected as a measured variable (Vmess, Imess) for the exerted force. The invention also relates to a membrane-based pressure sensor that uses a force sensor of this type, to a one- or two-dimensional position sensor that uses a plurality of force sensors of this type and to a fingerprint sensor that uses a plurality of force sensors of this type.
Abstract translation: 本发明涉及一种基于一个力传感器的基板上（1; 11）施加的有机场效应晶体管（10），其特征在于，作用在所述晶体管的机械力相应改变其源 - 漏电压或它的源极 - 漏极这些力中的一个的力 电流（ID）给出，其中各测量变量（VMEAS，Imess）是可检测的对所施加的力，一个这样的力传感器中使用基于膜的压力传感器，多个这样的力传感器的使用的一个或二维位置传感器和多个使用指纹传感器这样的力传感器。
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5.发明申请
公开(公告)号：WO0173617A8
公开(公告)日：2003-03-13
申请号：PCT/DE0100996
申请日：2001-03-15
Applicant: INFINEON TECHNOLOGIES AG , BREDERLOW RALF , PAULUS CHRISTIAN
Inventor： BREDERLOW RALF , PAULUS CHRISTIAN
CPC classification number: H01L22/20 , G06F17/5063
Abstract: The surface optimisation of components in integrated circuits with m components may be determined by a method comprising the following steps: fixing a pre-set repeat precision sigmaout; determination of the minimum surface area Ai for components of the circuit with a data processing unit; whereby the minimum surface area Ai of an i-th component in the circuit is determined by the following equation (I): where cij is a matching constant for the j-th of n electrical parameters with 1
Abstract translation: 一种用于在与具有如下步骤m个分量集成电路部件的空间优化方法，包括： - 设置预定重复性sigmaout; - 确定所述最小区域A I用于与数据处理系统中的电路的组件; （式1）其中CIJ为n个电参数的第j个的匹配常数与m的第i个分量的1 <= j的<= N：其中所述最小区域A i中的电路的第i个分量是由下式确定 用1部件<= I <=米; 和∂Sout/∂pij电气参数p ij的电路的输出信号Sout的偏导数。
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Patent Agency Ranking
公开(公告)号：WO03061004A2
公开(公告)日：2003-07-24
申请号：PCT/DE0300080
申请日：2003-01-13
Applicant: INFINEON TECHNOLOGIES AG , BREDERLOW RALF , ELBE ASTRID , KREUPL FRANZ , LUYKEN JOHANNES , NEUHAUSER ROBERT , PAULUS CHRISTIAN , SCHEPERS JOERG , THEWES ROLAND
Inventor： BREDERLOW RALF , ELBE ASTRID , KREUPL FRANZ , LUYKEN JOHANNES , NEUHAUSER ROBERT , PAULUS CHRISTIAN , SCHEPERS JOERG , THEWES ROLAND
IPC: G06K19/073 , H01L23/58 , H01L23/544
CPC classification number: B82Y10/00 , G06K19/073 , G06K19/07372 , H01L23/576 , H01L2223/5444 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
Abstract: According to the invention, an electrical characteristic of a material layer (3) or layer-type material structure is measured at various points provided with connection contacts (5, 6). A mean value of the measurement, taken from a base set of IC chips, is subtracted from a respective value, and a digital word for identifying the chip in question is formed on the basis of the result thus obtained, for each IC chip. The measurement can be carried out by means of a cross-correlation, the measuring regions crossing over each other.
Abstract translation: 一材料层（3）或所述材料的层状结构的电特性在不同的位置进行测定，与所述连接接点（5,6）被提供。 采取大约IC芯片平均测量的群的部分中的相应值的是由和由这样获得的结果，以每个IC芯片，一个数字字为各个芯片的识别中减去。 所述测量可以用互相关，其中，所述测量范围被交叉地设置制成。
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7.发明申请
公开(公告)号：WO0173617A3
公开(公告)日：2003-02-13
申请号：PCT/DE0100996
申请日：2001-03-15
Applicant: INFINEON TECHNOLOGIES AG , BREDERLOW RALF , PAULUS CHRISTIAN
Inventor： BREDERLOW RALF , PAULUS CHRISTIAN
CPC classification number: H01L22/20 , G06F17/5063
Abstract: The surface optimisation of components in integrated circuits with m components may be determined by a method comprising the following steps: fixing a pre-set repeat precision σout; determination of the minimum surface area Ai for components of the circuit with a data processing unit; whereby the minimum surface area Ai of an i-th component in the circuit is determined by the following equation (I): where cij is a matching constant for the j-th of n electrical parameters with 1
Abstract translation: 一种用于在与具有如下步骤m个分量集成电路部件的空间优化方法，包括： - 设置预定重复性σout; - 确定所述最小区域A I用于与数据处理系统中的电路的组件; （式1）其中CIJ为n个电参数的第j个的匹配常数与m的第i个分量的1 <= j的<= N：其中所述最小区域A i中的电路的第i个分量是由下式确定 用1部件<= I <=米; 和∂Sout/∂pij电气参数p ij的电路的输出信号Sout的偏导数。
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8.发明申请INTEGRATED CIRCUIT ARRANGEMENT AND METHOD FOR DETERMINING THE PARASITIC NON-REACTIVE RESISTANCE OF AT LEAST THE LEAD OF AT LEAST ONE MEMORY CELL OF AN INTEGRATED CIRCUIT ARRANGEMENT 审中-公开集成电路装置和方法用于确定所述寄生欧姆电阻至少供给所述至少一个小区集成电路装置的
公开(公告)号：WO2007093172A3
公开(公告)日：2007-11-15
申请号：PCT/DE2007000324
申请日：2007-02-16
Applicant: INFINEON TECHNOLOGIES AG , AUGUSTYNIAK MARCIN , BREDERLOW RALF , FREY ALEXANDER , HOLZAPFL BIRGIT , PAULUS CHRISTIAN , SAUERBREY JENS , SCHIENLE MEINRAD , THEWES ROLAND
Inventor： AUGUSTYNIAK MARCIN , BREDERLOW RALF , FREY ALEXANDER , HOLZAPFL BIRGIT , PAULUS CHRISTIAN , SAUERBREY JENS , SCHIENLE MEINRAD , THEWES ROLAND
CPC classification number: G11C29/02 , G01R27/14 , G01R31/2853 , G01R31/2884 , G11C11/401 , G11C29/025 , G11C29/50008
Abstract: An integrated circuit arrangement (300) has at least one electronic component (302), and also at least one resistance determining circuit that is coupled to the electronic component and is monolithically integrated with the latter and serves for determining the parasitic non-reactive resistance (303) of at least the lead to the at least one electronic component.
Abstract translation: 一种集成电路装置（300）具有至少一个电子部件（302），以及至少一个耦合到所述电子组件，并且该单片集成电阻确定电路，用于至少电源线确定所述至少一个寄生欧姆电阻（303） 电子组件。
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公开(公告)号：WO2005031973A2
公开(公告)日：2005-04-07
申请号：PCT/DE2004002079
申请日：2004-09-17
Applicant: INFINEON TECHNOLOGIES AG , BERTHOLD JOERG , BREDERLOW RALF , PACHA CHRISTIAN , VON ARNIM KLAUS
Inventor： BERTHOLD JOERG , BREDERLOW RALF , PACHA CHRISTIAN , VON ARNIM KLAUS
IPC: H03K19/017 , H03K19/096 , H03K
CPC classification number: H03K19/01728 , H01L2924/0002 , H03K19/0963 , H01L2924/00
Abstract: A clock transistor and a second operating potential functioning as a circuit breaker, are mounted between the outlet of an NMOS logic circuit.
Abstract translation: 在NMOS逻辑电路的输出之间，时钟晶体管和第二操作电位被切换，其充当断路器。
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10.发明申请
公开(公告)号：WO2004038770A3
公开(公告)日：2004-09-23
申请号：PCT/DE0303355
申请日：2003-10-10
Applicant: INFINEON TECHNOLOGIES AG , BREDERLOW RALF , HARTWICH JESSICA , PACHA CHRISTIAN , ROESNER WOLFGANG , SCHULZ THOMAS
Inventor： BREDERLOW RALF , HARTWICH JESSICA , PACHA CHRISTIAN , ROESNER WOLFGANG , SCHULZ THOMAS
IPC: H01L21/336 , H01L21/8242 , H01L21/84 , H01L27/06 , H01L27/108 , H01L27/12 , H01L29/786 , H01L21/02
CPC classification number: H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
Abstract: Disclosed is an integrated circuit arrangement (120), among others, comprising a transistor (122), preferably a FinFET, and a capacitor (124). The lower electrode of the capacitor (124) is disposed within an SOl substrate along with a channel section of the transistor (122). The inventive circuit arrangement (120) is easy to produce and has excellent electronic properties.
Abstract translation: 进行了说明，除其他外，集成电路装置（120）包括一个晶体管（122），优选地为所谓的FinFET，和电容器（124）。 电容器（124）的下部电极与在SOI衬底的晶体管（122）的沟道区布置在一起。 所述的电路装置（120）是容易制造并具有优良的电子特性。
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