公开(公告)号：DE102005009050A1

公开(公告)日：2006-09-07

申请号：DE102005009050

申请日：2005-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN GUNTHER ,  CHOSEROT VIANNEY ,  LARGUIER JEAN-YVES

IPC: G11C17/16 ,  G11C7/06

Abstract: A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells. The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells. The read-out circuit has a volatile signal memory, the inputs of which are connected to the read outputs of the memory cells.

公开(公告)号：DE102005009050B4

公开(公告)日：2007-01-11

申请号：DE102005009050

申请日：2005-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN GUNTHER ,  CHOSEROT VIANNEY ,  LARGUIER JEAN-YVES

IPC: G11C17/16 ,  G11C7/06

Abstract: A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells. The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells. The read-out circuit has a volatile signal memory, the inputs of which are connected to the read outputs of the memory cells.