公开(公告)号：DE10109486A1

公开(公告)日：2002-09-12

申请号：DE10109486

申请日：2001-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SZCZYPINSKI KAZIMIERZ ,  FISCHER HELMUT ,  CHRYSOTOMIDES ATHANASIA

IPC: G11C11/4097 ,  H01L27/108 ,  G11C7/06 ,  G11C7/18

Abstract: The invention relates to an integrated DRAM memory chip comprising sense amplifiers, each configured for the integrated module from a large number of transistor structures and signal conduction pathway structures that are arranged in a regular pattern in cell fields. Said structures comprise amplifier transistors for amplifying the bit line signal, which are structurally identical and lie opposite one another in pairs in neighbouring transistor rows, and signal conduction pathways that are assigned to the transistor rows, running parallel with the latter, for supplying control signals. According to the invention, the signal conduction pathways for the control signals have the same configuration symmetry as the amplifier transistors, in such a way that the amplifier transistors of neighbouring transistor rows have the same proximity to the signal conduction pathway.

公开(公告)号：DE10109486B4

公开(公告)日：2006-01-05

申请号：DE10109486

申请日：2001-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SZCZYPINSKI KAZIMIERZ ,  FISCHER HELMUT ,  CHRYSOTOMIDES ATHANASIA

IPC: G11C7/06 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/108 ,  H03K3/356 ,  H03K17/687

Abstract: An integrated DRAM memory component has sense amplifiers which, respectively within the framework of the integrated component, are formed from a multiplicity of transistor structures, arranged regularly in cell arrays, and signal interconnect structures with amplification transistors for bit line signal amplification. The amplification transistors are of identical design and they lie opposite one another in pairs in adjacent transistor rows. Signal interconnects, which are associated with the transistor rows and run parallel thereto, supply actuation signals. The signal interconnects for the actuation signals have the same arrangement symmetry as the amplification transistors, which means that the amplification transistors in adjacent transistor rows are in the same signal interconnect proximity.