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    METHOD AND DEVICE FOR REDUCING ELECTRIC CURRENT CONSUMPTION IN ELECTRONIC CIRCUIT
    1.
    发明专利
    METHOD AND DEVICE FOR REDUCING ELECTRIC CURRENT CONSUMPTION IN ELECTRONIC CIRCUIT 审中-公开

    公开(公告)号：JP2003185709A

    公开(公告)日：2003-07-03

    申请号：JP2002270707

    申请日：2002-09-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  PFEIFFER JOHANN ,  SCHNABEL RAINER FLORIAN

    IPC: G01R31/28 ,  G11C11/401 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  H01L21/822 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To reduce an electric current consumption in an operation time of an electronic circuit caused by a test module for testing the electronic circuit. SOLUTION: The present invention relates to a method of reducing the electric current consumption in the electronic circuit. The electronic circuit has the at least one test module 30 provided for testing the electronic circuit, and connected to at least one wire 38, 40 and/or one terminal of the electronic circuit. One test control signal 34 is generated, the at least one test module 30 is electrically separated at least partially from the at least one wire 38, 40 and/or the at least one terminal in an operation mode of the electronic circuit, using the test control signal, and a switching current is evaded in the at least one test module. COPYRIGHT: (C)2003,JPO

    INTEGRATED CIRCUIT
    3.
    发明专利
    INTEGRATED CIRCUIT 失效

    公开(公告)号：JP2001229676A

    公开(公告)日：2001-08-24

    申请号：JP2001004181

    申请日：2001-01-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  KUHNE SEBASTIAN ,  LE THOAI-THAI

    IPC: G11C11/409 ,  G11C11/407 ,  H03F3/45 ,  H03K19/0944

    Abstract: PROBLEM TO BE SOLVED: To improve an integrated circuit by selecting a MOS transistor and supplying stable voltage. SOLUTION: A differential amplifier 1 has two input transistors T1, T2, a load element 2, and a current source 3 having a N channel MOS transistor T3, a section to be controlled of the transistor is connected to an input transistor and a current source supply connection terminal 31, and a control connection terminal G is connected to a connection terminal of a potential V3 being positive for a reference potential GND. An integrated circuit is inclined in a circuit device of a dynamic memory, the supply connection terminal of the current source is connected to a voltage source 4 for cutting off an array panel transistor of an integrated dynamic memory, and the voltage source has a negative potential V2 for the reference potential.

    INTEGRATED DRAM MEMORY CHIP
    4.
    发明申请
    INTEGRATED DRAM MEMORY CHIP 审中-公开
    集成DRAM存储设备

    公开(公告)号：WO02069407A3

    公开(公告)日：2003-10-02

    申请号：PCT/EP0201593

    申请日：2002-02-14

    Applicant: INFINEON TECHNOLOGIES AG ,  CHRYSOSTOMIDES ATHANASIA ,  SZCZYPINSKI KAZIMIERZ ,  FISCHER HELMUT

    Inventor： CHRYSOSTOMIDES ATHANASIA ,  SZCZYPINSKI KAZIMIERZ ,  FISCHER HELMUT

    IPC: G11C11/4097 ,  H01L27/108

    CPC classification number: G11C11/4097 ,  H01L27/10897

    Abstract: The invention relates to an integrated DRAM memory chip comprising sense amplifiers, each configured for the integrated module from a large number of transistor structures and signal conduction pathway structures that are arranged in a regular pattern in cell fields. Said structures comprise amplifier transistors for amplifying the bit line signal, which are structurally identical and lie opposite one another in pairs in neighbouring transistor rows, and signal conduction pathways that are assigned to the transistor rows, running parallel with the latter, for supplying control signals. According to the invention, the signal conduction pathways for the control signals have the same configuration symmetry as the amplifier transistors, in such a way that the amplifier transistors of neighbouring transistor rows have the same proximity to the signal conduction pathway.

    Abstract translation: 本发明涉及一种分别形成为布置在单元阵列晶体管的结构和信号的互连结构的多个规则的集成模块的一部分的集成具有DRAM存储器装置读出放大器，放大晶体管为Bitleitungssignalverstärkung是相反在相邻晶体管行结构上彼此相同，并且在对， 和分配给该晶体管的行包括用于提供驱动信号，这些并行信号互连。 根据本发明，提供的是具有相同的结构增益晶体管的对称性的驱动信号的信号线路路径，使得晶体管的增益相邻晶体管的行是在同一信号通路附近。

    METHOD FOR READING A MEMORY CELL OF A SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR MEMORY
    5.
    发明申请
    METHOD FOR READING A MEMORY CELL OF A SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR MEMORY 审中-公开
    方法用于读取半导体存储器半导体存储器的存储单元

    公开(公告)号：WO02067264A3

    公开(公告)日：2003-02-27

    申请号：PCT/DE0200486

    申请日：2002-02-11

    Applicant: INFINEON TECHNOLOGIES AG ,  FISCHER HELMUT ,  SZCZYPINSKI KAZIMIERZ

    Inventor： FISCHER HELMUT ,  SZCZYPINSKI KAZIMIERZ

    IPC: G11C11/409 ,  G11C7/06 ,  G11C11/401 ,  G11C7/12

    CPC classification number: G11C7/06

    Abstract: The invention relates to a semiconductor memory wherein the substantially parallel bit lines (38, 39) are capacitatively coupled with one another. Outer sections (13, 14, 36, 37) of said bit lines are linked with an interposed sense amplifier (10) via respective switches (27, 28, 29, 30). The aim of the invention is to keep to a minimum the capacitative coupling of other bit lines into the bit line (39) not coupled to the memory cell (15) to be read out during read-out of a memory cell (15) before the sense amplifier (10) starts amplification. To this end, the switches (28, 29) in said bit line (39) are in the position in which they are conducting. During the amplification phase the remote outer section (37) of said bit line (39) is switched off via the respective switch (29). In an embodiment of the invention, the capacity of the bit line (39) linked with the memory cell (15) to be read out is increased even further by additionally activating a precharge circuit (31).

    Abstract translation: 在半导体存储器中，存在很大程度上平行的位线（38，39）之间的电容耦合。 位线的外部部分（13，14，36，37）通过相应的开关（27，28，29，30）与所述插入的读出放大器（10）相连接。 至28读取放大的通过与所述存储器单元中的非读出放大器（10）开始之前的存储单元（15）时（15）的位线（39）以最小化，开关由其它位线连接的电容性耦合（ ，开关29）的导电的那些位线（39）。 在扩增阶段期间经由相应的开关（29），所述位线（39）的远程外部部分（37）被关闭。 在一个实施例中，与连接到该位线（39）的存储单元（15）非的电容进一步增大通过提供的预充电电路（31）也被激活。

    6.
    发明专利
    未知

    公开(公告)号：DE10224180B4

    公开(公告)日：2007-01-04

    申请号：DE10224180

    申请日：2002-05-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MENCZIGAR ULLRICH ,  FISCHER HELMUT

    IPC: H01L27/08 ,  H01L23/522 ,  H01L23/58 ,  H01L23/64 ,  H01L27/06

    Abstract: An RC network is integrated in a semiconductor circuit chip and is connected between an input pad or pin and a ground node coupled to a substrate of the chip. The RC network has a plurality of resistance elements, a plurality of capacitance elements and a plurality of connection/isolation elements, which are provided in each case between at least one of the resistance elements and the individual capacitive elements. The inventive circuit configuration enables an optional and independent setting of the input capacitance and of the input resistance of the semiconductor circuit chip, depending on the connection/isolation state of the connection/isolation elements.

    9.
    发明专利
    未知

    公开(公告)号：DE10226485A1

    公开(公告)日：2005-06-23

    申请号：DE10226485

    申请日：2002-06-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

    IPC: G11C11/408 ,  G11C8/12

    Abstract: A semiconductor memory includes: at least two memory banks that each have a memory cell matrix, an address decoding unit which includes a bank address decoding unit, a row address decoding unit and a column address decoding unit. At least one demultiplexer is connected upstream of the address buffer memories provided in the row address decoding unit and/or in the column address decoding unit. This demultiplexer is connected to the bank address decoder in order, on the basis of the decoded bank address, to activate the corresponding address buffer memory.

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