公开(公告)号：WO02078058A3

公开(公告)日：2003-06-26

申请号：PCT/DE0200732

申请日：2002-02-28

Applicant: INFINEON TECHNOLOGIES AG ,  CAPPELLANI ANNALISA ,  DITTMAR LUDWIG ,  SCHUMANN DIRK

Inventor： CAPPELLANI ANNALISA ,  DITTMAR LUDWIG ,  SCHUMANN DIRK

IPC: H01L21/3065 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/28114 ,  H01L21/2652 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28123 ,  H01L21/32137 ,  H01L29/66575

Abstract: The invention relates to a method, whereby a gate layer stack consisting of at least two layers (3 and 5) is initially structured anisotropically and the bottom layer (3) is then etched, wherein an isotropic, preferably a selective etching step causes lateral underetching, i.e. removal of the bottom layer (3) to a predetermined channel length. A T-Gate transistor with very short channel length can be accurately, easily and economically produced with the aid of the inventive method. The electrical switching properties of said transistor are better than those of other T-gate transistors formed with conventional methods.

Abstract translation: 本发明公开了一种方法，其中至少两个层（3）和（5）存在的栅极层堆叠第一各向异性图案化，然后将下层（3）进行蚀刻的各向同性，优选选择性蚀刻步骤，一个侧面蚀刻，D。 小时。 实现除去下层（3）的所述预定信道长度。 利用本发明的方法的帮助下，一个T栅极晶体管非常短的沟道长度可以尺寸精确的，被制造和很容易地花费。 其电气开关性质比其他的，通过常规的方法T-栅极晶体管形成更好。

公开(公告)号：DE50205651D1

公开(公告)日：2006-04-06

申请号：DE50205651

申请日：2002-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CAPPELLANI ANNALISA ,  DITTMAR LUDWIG ,  SCHUMANN DIRK

IPC: H01L21/28 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/78

Abstract: A gate layer stack formed with at least two layers is firstly patterned anisotropically and then thelower layer is etched. An isotropic, preferably selective etching step effects a lateral undercutting, i.e. removal of the lower layer as far as the predetermined channel length to form a dimensionally accurate T-gate transistor with a very short channel length.

公开(公告)号：DE10229188A1

公开(公告)日：2004-01-29

申请号：DE10229188

申请日：2002-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUSTIN WOLFGANG ,  STEGEMANN MAIK ,  DITTMAR LUDWIG

IPC: H01L21/768 ,  H01L21/283 ,  H01L21/8242

Abstract: The invention relates to a method for contacting parts of a component integrated into a semiconductor substrate ( 1 ). According to the inventive method, a first contact hole is produced in an insulating layer ( 2 ), said contact hole being then filled with contact material ( 16 ) and connected to a line. The aim of the invention is to minimise the processes required for contacting parts of a component integrated into a semiconductor substrate. To this end, the hard mask ( 3 ) used to produce the contact hole is also used to structure the line.

公开(公告)号：DE10114778A1

公开(公告)日：2002-10-17

申请号：DE10114778

申请日：2001-03-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CAPPELLANI ANNALISA ,  DITTMAR LUDWIG ,  SCHUMANN DIRK

IPC: H01L21/3065 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/78

Abstract: A gate layer stack formed with at least two layers is firstly patterned anisotropically and then thelower layer is etched. An isotropic, preferably selective etching step effects a lateral undercutting, i.e. removal of the lower layer as far as the predetermined channel length to form a dimensionally accurate T-gate transistor with a very short channel length.