公开(公告)号：JP2006148122A

公开(公告)日：2006-06-08

申请号：JP2005335579

申请日：2005-11-21

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： BACHMANN JENS ,  DONOHUE LEE ,  EFFERENN DIRK ,  GOTTZEIN RONALD ,  KAHLER UWE ,  LIN CHUNG-HSIN ,  LIN WEN-BIN

IPC: H01L21/304 ,  H01L21/3065

CPC classification number: G03F7/427 ,  C23G5/00 ,  H01J37/32192 ,  H01J2237/3342 ,  H01L21/02071

Abstract: PROBLEM TO BE SOLVED: To provide a method for removing residues containing a polymer resist and a metal oxide from a metal structure on a semiconductor substrate, in the semiconductor substrate on which metal wiring is formed.
SOLUTION: The method includes a heating step (a) of heating the substrate having the metal structure under the presence of nitrogen (N
2 ), a stabilizing step (b) of stabilizing under the presence of pure nitrogen (N
2 ), a passivating step (c) of passivating by using a plasma containing at least one of water, nitrogen and oxygen, and an exfoliating step (d) using oxygen to remove the residue containing the resist.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在形成金属布线的半导体衬底中从半导体衬底上的金属结构去除含有聚合物抗蚀剂和金属氧化物的残留物的方法。 解决方案：该方法包括在氮气存在下加热具有金属结构的基材的加热步骤（a），在存在下稳定的稳定步骤（b） 的纯氮（N 2 ），通过使用含有水，氮和氧中的至少一种的等离子体进行钝化的钝化步骤（c），和使用氧气去除 含有抗蚀剂的残渣。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004179665A

公开(公告)日：2004-06-24

申请号：JP2003398862

申请日：2003-11-28

Applicant: Infineon Technologies Ag ,  インフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER

IPC: H01L21/76 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867

Abstract: PROBLEM TO BE SOLVED: To prevent a shrink hole from being formed in a filling material to be embedded in an insulated trench in a memory cell semiconductor structure equipped with trench capacitors.
SOLUTION: Two or more trenches are provided in a semiconductor substrate 10 by using a first hard mask 50, a capacitor plate 20 is formed by embedding polysilicon, then after the first hard mask 50 is moved backward by a predetermined distance, a second hard mask is formed in such a manner as to overlap part of the first hard mask and at the same time extend on the polysilicon in the trench beyond the first hard mask, a shallow insulated trench structure ST having a small aspect ratio is formed by the use of the second hard mask by etching part of the polysilicon in each trench and the semiconductor substrate between trenches in such a manner as to span the two trenches, and after the second mask is removed, the trench structure ST is filled with the filling material FI for flattening.
COPYRIGHT: (C)2004,JPO

公开(公告)号：DE10139430B4

公开(公告)日：2005-09-15

申请号：DE10139430

申请日：2001-08-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER ,  GRUENING ULRIKE

IPC: H01L21/762 ,  H01L21/8242

公开(公告)号：DE10139431A1

公开(公告)日：2003-03-06

申请号：DE10139431

申请日：2001-08-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER

IPC: H01L21/762 ,  H01L21/8242

Abstract: Production of isolation trenches between active regions during the manufacture of integrated circuits, especially DRAMs, comprises etching trenches filled with an oxide in a semiconductor substrate (10) to isolate the active regions and form deep trenches (12) filled with polysilicon (14); forming a silicon nitride layer (18) on the surface of the substrate; applying an oxide layer (20) on the surface of the substrate and the polysilicon by plasma deposition with back-sputtering; and back-etching the oxide layer to expose the surface of the nitride and selectively removing the nitride. Preferred Features: The back-etching is a high density plasma deposition process.

公开(公告)号：DE10255686B3

公开(公告)日：2004-07-15

申请号：DE10255686

申请日：2002-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER

IPC: H01L21/76 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

Abstract: An isolation trench structure (ST) is formed on a semiconductor substrate (10) using a hard mask (HM) made of silicon oxide, such that the strip sections (501', 503') on the substrate are offset with respect to each other. The overlap region (KB') between the strip sections is reduced, and the trench structure is filled with a material containing silicon oxide.

公开(公告)号：DE10139431C2

公开(公告)日：2003-06-18

申请号：DE10139431

申请日：2001-08-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER

IPC: H01L21/762 ,  H01L21/8242

公开(公告)号：DE10141839A1

公开(公告)日：2002-11-14

申请号：DE10141839

申请日：2001-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER

IPC: H01L21/3105 ,  H01L21/316 ,  H01L21/321 ,  H01L21/308 ,  H01L21/311

Abstract: Production of a self-adjusting mask for a first structure (1) arranged at a distance from a second structure (2) comprises covering the structures with a covering layer (4); applying a further covering layer (20) of constant thickness; removing the further covering layer until the first covering layer is exposed in a first partial surface (21); and removing the covering layer in the region of the first partial surface until the first structure is exposed. Preferred Features: The covering layer (4) is made from silicon oxide and is deposited using a plasma deposition process, in which a pressure of 2-20 mTorr prevails during deposition. The further covering layer is made from a polysilicon layer. The further covering layer is removed using chemical/mechanical polishing.

公开(公告)号：DE10302544A1

公开(公告)日：2004-08-05

申请号：DE10302544

申请日：2003-01-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER

IPC: B81C1/00 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/3215

Abstract: Production of a hard mask on a semiconductor substrate (1) comprises forming a hard mask layer (2) on the substrate, forming a photolacquer structure on the hard mask layer, inserting a dopant in the hard mask layer in the surface regions of the photolacquer structure, removing the photolacquer structure from the hard mask layer, and etching the hard mask layer using an etchant to open the hard mask layer only in the non-doped regions (31).

公开(公告)号：DE10210434A1

公开(公告)日：2003-10-23

申请号：DE10210434

申请日：2002-03-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER ,  WICH-GLASEN ANDREAS

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/8242

Abstract: The method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module provides the following steps. A thermal oxide layer is applied in isolation trenches. A nitride liner is subsequently applied. In a further step, a mask is applied in the region in which n-channel field-effect transistors are intended to be produced. The nitride liner is removed around the mask. Finally, the mask is also removed. As a result, the properties of the n-channel field-effect transistors are improved, without impairing the properties of the p-channel field-effect transistors.

公开(公告)号：DE10201178A1

公开(公告)日：2003-06-26

申请号：DE10201178

申请日：2002-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EFFERENN DIRK ,  MOLL HANS-PETER

IPC: H01L21/033 ,  H01L21/31 ,  B81C1/00 ,  G03F9/00 ,  H01L21/027 ,  H01L21/469 ,  H05K3/00

Abstract: Masking first recesses of a structure having large aspect ratio comprises applying filler layer (5) so that a hollow space (6) is formed in first recesses, and removing filler layer up to hollow space region by etching. Etching is also carried out in hollow space, and filler layer is removed more quickly from first recesses than from further recesses. Etching process is stopped after removing filler layer from first recesses. Preferred Features: The etching process is an isotropic etching process. The structure has connectors (4) having a sacrificial layer applied on the surface before applying the filler layer. The filler layer is a silicon oxide layer deposited using a TEOS process.