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    METHOD FOR PRODUCING AN INTEGRATED SEMICONDUCTOR COMPONENT
    1.
    发明申请
    METHOD FOR PRODUCING AN INTEGRATED SEMICONDUCTOR COMPONENT 审中-公开
    方法用于制造集成半导体COMPONENT

    公开(公告)号：WO0241399A3

    公开(公告)日：2002-08-15

    申请号：PCT/EP0112034

    申请日：2001-10-17

    Applicant: INFINEON TECHNOLOGIES AG ,  MOLL HANS-PETER ,  WICH-GLASEN ANDREAS ,  TRUEBY ALEXANDER

    Inventor： MOLL HANS-PETER ,  WICH-GLASEN ANDREAS ,  TRUEBY ALEXANDER

    IPC: H01L21/762

    CPC classification number: H01L21/76224 ,  Y10S438/928 ,  Y10S438/976

    Abstract: The invention relates to a method for producing an integrated semiconductor component (1). At least one isolation trench is formed, a first layer (4) consisting of a non-conductive material is applied by means of a non-conforming deposition process, and a second layer (5) consisting of a non-conductive material is applied at least to the rear side of the semiconductor component by means of a conforming deposition process.

    Abstract translation: 本发明公开了用于制造集成半导体器件1，其中，在形成至少一个隔离沟槽的方法中，第一层4由非导电材料由一非共形沉积方法，并通过非导电材料的第二层5涂覆 共形沉积方法，至少施加到半导体器件的背面。

    DRAM MEMORY CELL WITH A TRENCH CAPACITOR AND METHOD FOR PRODUCTION THEREOF
    2.
    发明申请
    DRAM MEMORY CELL WITH A TRENCH CAPACITOR AND METHOD FOR PRODUCTION THEREOF 审中-公开
    根据上述制造坟墓电容器和方法DRAM单元

    公开(公告)号：WO02101824A3

    公开(公告)日：2003-08-28

    申请号：PCT/DE0202046

    申请日：2002-06-05

    Applicant: INFINEON TECHNOLOGIES AG ,  RICHTER FRANK ,  TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

    Inventor： RICHTER FRANK ,  TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10867 ,  H01L27/10832 ,  H01L27/10873

    Abstract: A memory cell (10) is embodied with a selection transistor (60) and a trench capacitor (30). The trench capacitor (30) is filled with a conducting trench filling (35), upon which an insulating cover layer (40) is arranged. A selectively grown epitaxial layer (45) is laterally grown over the insulating cover layer, starting from the substrate (15). The selection transistor (60) is embodied in the selectively grown epitaxial layer (45) and comprises a source region (65), for connection to the trench capacitor (30) and a drain region (70) for connection to a bitline. The junction depth of the source region (65) is selected such that the source region (65) extends as far as the insulating cover layer (40). In addition the thickness (50) of the epitaxial layer (45) may be optionally reduced to a suitable thickness by means of an oxidation and a subsequent etching. A contact trench (95) is then etched through the source region (65) as far as the conducting trench filling (35), which is filed with a conducting contact (90) and the conducting trench filling (35) electrically connected to the source region (65).

    Abstract translation: 形成有具有选择晶体管（60）和一个电容器严重（30）的存储单元（10）。 坟墓电容器（30）被填充有导电填充严重（35），在其上的绝缘层（40）被布置。 覆盖绝缘层是横向地，从基板（15）配有一个选择性地生长外延层（45）生长开始。 在选择晶体管的选择性生长的外延层（45）（60）形成，并且在这种情况下包括连接到位线的源极区（65）以与严重电容器（30）连接，并且漏极区域（70） 要被连接的。 源极区（65）的结深度现在被选择为使得源极区（65）延伸直到所述绝缘覆盖层（40）。 任选地，通过氧化和随后的蚀刻的装置的外延层（45）的厚度（50）可以减少到适当的厚度。 接着，通过接触沟槽（95），以在导电严重填充所述源极区（65）（35）被蚀刻时，其被填充有导电接触（90）和所述导电严重填充（35）电性（与源极区域 65）连接。

    METHOD FOR BROADENING ACTIVE SEMICONDUCTOR AREAS
    4.
    发明申请
    METHOD FOR BROADENING ACTIVE SEMICONDUCTOR AREAS 审中-公开
    方法增有源半导体区

    公开(公告)号：WO02071474A3

    公开(公告)日：2002-11-28

    申请号：PCT/EP0201786

    申请日：2002-02-20

    Applicant: INFINEON TECHNOLOGIES AG ,  TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

    Inventor： TEMMLER DIETMAR ,  WICH-GLASEN ANDREAS

    IPC: H01L21/762

    CPC classification number: H01L21/76235

    Abstract: The invention relates to a method for broadening active semiconductor areas (2) on a semiconductor substrate (1) that has at least one trench isolation (3). The method is composed of the following steps: deposition of a pad-oxide layer (5) on a surface (4) of the semiconductor substrate (1); deposition of a pad-nitride layer (6) on the pad-oxide layer (5); structuring of the pad-nitride layer (6) to create at least one opening in the pad-nitride layer (6) and etching of the trench isolation(s) (3) in the pad-oxide layer (5) and the semiconductor substrate (1). The aim of the invention is to adjust the broadening of the structures of active semiconductor areas in a simple and cost-effective manner that is substantially independent of other process steps during the production of the component. To achieve this, the inventive method is characterised by the selective deposition of an epitaxy layer (7) with a predetermined thickness and by the oxidation of the surface (4) of the semiconductor substrate (1), to create a thin oxide layer (9) for passivation.

    Abstract translation: 本发明涉及一种用于（2）在半导体衬底上加宽的有源半导体区域（1）具有至少一个严重绝缘（3），下裆个，在一个Oberflä枝沉积垫氧化物层（5）（4） 在半导体基板（1）; 衬垫氧化物层上沉积垫氮化物层（6）（5）; 在垫氮化物层（6），产生至少一个截止电压以及蚀刻所述至少一个严重绝缘（3）在焊盘氧化物层（5）和在所述半导体衬底进行构图的衬垫氮化物层（6）（1）。到 结构宽度的有源半导体区域，以独立于其它工艺步骤SET-LEN在器件的制造中以简单和成本有效的方式基本上，本发明的方法被标记在通过选择性地沉积具有预定厚度的外延层（7）和氧化表面（4 ），用于生成用于钝化的薄O型xidschicht（9）的半导体衬底（1）的。

    5.
    发明专利
    未知

    公开(公告)号：DE10123770A1

    公开(公告)日：2002-12-05

    申请号：DE10123770

    申请日：2001-05-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WICH-GLASEN ANDREAS ,  TEMMLER DIETMAR ,  SCHREMS MARTIN

    IPC: H01L21/60 ,  H01L21/8242 ,  H01L27/108

    Abstract: The instant invention is a method for fabricating a trench contact to a deep trench capacitor with a polysilicon filling in a trench hole formed in a silicon substrate. An epitaxy process is performed to selectively grow silicon above the polysilicon filling in the trench hole. An opening leading to the polysilicon filling is anisotropically etched into the epitaxially grown silicon. The opening has lateral dimensions that are smaller than those of the polysilicon filling, and the opening is filled with polysilicon.

    7.
    发明专利
    未知

    公开(公告)号：DE10131237B8

    公开(公告)日：2006-08-10

    申请号：DE10131237

    申请日：2001-06-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TEMMLER DIETMAR ,  RICHTER FRANK ,  POPP MARTIN ,  WICH-GLASEN ANDREAS

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

    Abstract: A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current I ON can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.

    10.
    发明专利
    未知

    公开(公告)号：DE10056261A1

    公开(公告)日：2002-05-29

    申请号：DE10056261

    申请日：2000-11-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TRUEBY ALEXANDER ,  WICH-GLASEN ANDREAS ,  MOLL HANS-PETER

    IPC: H01L21/762

    Abstract: The invention relates to a method for producing an integrated semiconductor component (1). At least one isolation trench is formed, a first layer (4) consisting of a non-conductive material is applied by means of a non-conforming deposition process, and a second layer (5) consisting of a non-conductive material is applied at least to the rear side of the semiconductor component by means of a conforming deposition process.

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