公开(公告)号：WO0158010A3

公开(公告)日：2002-12-27

申请号：PCT/DE0100238

申请日：2001-01-19

Applicant: INFINEON TECHNOLOGIES AG ,  ENGL BERNHARD

Inventor： ENGL BERNHARD

IPC: G11C27/02 ,  H03F3/45 ,  H03M1/10 ,  H03M1/36 ,  H03M1/06

CPC classification number: H03M1/1014 ,  G11C27/026 ,  H03F3/45753 ,  H03F3/45771 ,  H03F2200/331 ,  H03F2203/45048 ,  H03M1/141

Abstract: The inventive amplifier stage calibration comprises the following steps: creating conditions that are suitable for calibrating the amplifier stage; comparing signals output by the amplifier stage or comparing electrical quantities occurring inside the amplifier stage with one another or with assigned reference values, and; modifying the attributes of the amplifier stage based on the result of the comparison. The described compensation of errors in amplifier stages of series-connected components is effected by correspondingly calibrating the amplifier stage. The inventive devices and methods enable the calibration of amplifier stages and the compensation for errors in amplifier stages of series-connected components to be carried out rapidly and precisely in an astonishingly simple manner.

Abstract translation: 所描述的放大器级校准包括以下步骤：为所述放大器级的条件的校准创建权宜之计，比较所述放大器级的信号的输出或与彼此或与相关联的基准值的放大器级的电气量内发生，并且改变所述放大器级的要被校准特性的函数 该比较的结果。 为在放大器的误差补偿级描述通过放大器级的适当的校准发生上游部件。 所描述的装置和方法描述了放大器级的校准和在放大器级中的错误一个非常简单的方式上游部件被快速，准确地进行补偿。

公开(公告)号：WO03044945A2

公开(公告)日：2003-05-30

申请号：PCT/EP0210596

申请日：2002-09-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGL BERNHARD

IPC: H03K5/24 ,  H03F3/00

CPC classification number: H03K5/2481 ,  H03K5/249

Abstract: The invention relates to a multiphase comparator, comprising a first difference stage (2) and a regeneration stage (4A,4B), whereby the first difference stage (2) amplifies an input signal in a first clock phase and supplies the same to a load element (5A) and the regeneration stage (4A) further amplifies the input signal. According to the invention, the effective comparison phase may be increased, whereby a first switching arrangement (3), which can selectively connect the output (AM,AP) from the first difference stage (2) with the input (RMi,RPi) of several load circuits (5A,5B), at least two regeneration stages (4A,4B), which are connected to one of the load circuits (5A,5B) and the switch arrangement (3) and a clock-controlled, second switch arrangement (6) are provided in order to supply the at least two regeneration stages (4A,4B) with an operating current which can be switched on and off. The switches for the first and second switch arrangement (3,6) are controlled such that the regeneration stages (4A,4B) operate with a temporal displacement.

Abstract translation: 本发明涉及一种具有一个第一差动级的多相位比较器（2）和再生阶段（4A，4B），其中所述第一差动级（2）放大在第一时钟相位的输入信号和一个负载元件（5A）的结果，和再生阶段（4A ）进一步放大的输入信号。 为了增加有效Komparierungsphase第一开关装置（3）连接所述第一差动级（2）的输出端（AM，AP）提出了多个负载电路（5A，5B）可以选择性地连接到所述输入（RM I，RP i）中，至少有两个 再生阶段（4A，4B）连接至所述负载电路中的一个（5A，5B）和所述开关装置（3）相连接，并且一个时钟控制的，第二开关装置（6）提供给所述至少两个再生阶段（4A，4B）具有TO- 供应和关断工作电流，第一和第二开关装置（3,6）的开关被控制以使再生阶段（4A，4B）在时间零点偏移。

公开(公告)号：WO02057864A2

公开(公告)日：2002-07-25

申请号：PCT/DE0200111

申请日：2002-01-16

Applicant: INFINEON TECHNOLOGIES AG ,  ENGL BERNHARD

Inventor： ENGL BERNHARD

IPC: G05F3/24 ,  G05F3/00

CPC classification number: G05F3/242

Abstract: The invention relates to a current source circuit that is characterized in that it comprises a control device (T2', T11', T12', T6, IQ1, IQ2) which controls a component (T2) of the current source circuit which determines a variable of the current supplied by the current source circuit, and in that the component is controlled in accordance with the conditions that prevail in the unit that supplied by the current source circuit with current. The inventive circuit is thus capable of continuously supplying a constant current without any limitations to its applications.

Abstract translation: 所描述的电流源电路的特征在于，包括电流源电路，一个控制装置（T2“ T11' ，T12”，T6，IQ1，IQ2），它是输出的大小由电流源电路的电流确定部件（T2）控制的电流源电路， 并且控制根据哪个为准，与电源单元中的电流源电路的供给的条件下进行。 这样，可实现的是，相同的电流源电路总是提供恒定的电流，不限制应用的可能性。

公开(公告)号：WO0161861A3

公开(公告)日：2002-04-25

申请号：PCT/EP0101521

申请日：2001-02-12

Applicant: ENGL BERNHARD ,  MENKHOFF ANDREAS ,  INFINEON TECHNOLOGIES AG

Inventor： ENGL BERNHARD ,  MENKHOFF ANDREAS

IPC: H03M1/10 ,  H03M1/12 ,  H03M1/36

CPC classification number: H03M1/1038 ,  H03M1/1023 ,  H03M1/12 ,  H03M1/368

Abstract: An analog/digital converter circuit comprises an analog/digital converter (1) and calibrating agents, preferably in the form of a digital logic, for the auto-calibration of the analog/digital converter (1). This configuration produces a very high quality analog/digital converter (1) with a very low surface area requirement. According to a first embodiment, the calibrating means (2-4) correct any error of the analog/digital converter (1) outside of said analog/digital converter (1). According to a second example of an embodiment, the correction is made inside the analog/digital converter.

公开(公告)号：DE10259070A1

公开(公告)日：2004-07-15

申请号：DE10259070

申请日：2002-12-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGL BERNHARD

IPC: H03K3/356 ,  H03K17/693 ,  H03K21/08

Abstract: A clock divider comprises a clock input (TE,PH1,PH2) and at least two clock outputs (T1,T2) to output signals of lower clock rate than the inputs. A circuit controls the energy supply so that the output circuit is only activated when needed depending on the input signal. An Independent claim is also included for a demultiplexer circuit having many outputs comprising the above.

公开(公告)号：DE10245210A1

公开(公告)日：2004-04-15

申请号：DE10245210

申请日：2002-09-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGL BERNHARD

IPC: H04J3/04 ,  H04J3/06 ,  H04L5/00

Abstract: A demultiplexer arrangement has several first demultiplexer stages (12) to which are supplied the scanning values of a correspondingly scanned signal (RX) with a corresponding scanning clock (11). Each of the demultiplexer stages (12) has at least one clock divider (13) and circuit devices (14,15) for outputting the respective supplied scanning values (10). At least one second demultiplexer stage (not shown here) receives the scanning values (QA,QB) outputted by the first stages (12) and combines them to a scanned word (SDQ). A phase correction device (not shown) receives the divided scanned clock-pulses (CLK,CLKB) of the first demultiplexer stage (12) and is designed so that the position of the scanning phases of the divided scanned clock-pulses to one another is ascertained and generates clock signals dependent on this position for the at least second demultiplexer stage. An Independent claim is included for a CDR- circuit arrangement for clock- and data-recovery.

公开(公告)号：DE10156817C1

公开(公告)日：2003-05-28

申请号：DE10156817

申请日：2001-11-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGL BERNHARD

IPC: H03K5/24

公开(公告)号：DE10042584A1

公开(公告)日：2002-03-28

申请号：DE10042584

申请日：2000-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGL BERNHARD

IPC: H03M1/06 ,  H03M1/36 ,  H03M1/12 ,  H03F3/45

Abstract: The input stage of analog-to-digital converter includes differential amplifiers (DP11,DP12,DN13,DN14). First and second transistors (TP11,TP12) of at least one amplifier (DP11,DP12) are complementary to first and second transistors (TN11,TN12) of the other amplifier (DN13,DN14).

公开(公告)号：DE50115449D1

公开(公告)日：2010-06-02

申请号：DE50115449

申请日：2001-01-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGL BERNHARD

IPC: G01R35/00 ,  G11C27/02 ,  H03F3/45 ,  H03M1/06 ,  H03M1/10 ,  H03M1/36

Abstract: A folding stage of the convertor has means for sensitizing, inhibiting and enabling signal paths through the convertor such that in a first operating condition, first and second inputs to the stage are switched through to corresponding inputs of a differential amplifier (3) of the respective stage. In a second operating condition a low auxiliary potential is applied to the first input and a high auxiliary potential is applied to the second input. In a third condition a high auxiliary potential is applied to the first input and a low auxiliary potential is applied to the second input. In a fourth condition both inputs are set to a potential between the high and low potentials. Means (13) are also provided to set the amplifier outputs to the same potential in dependence on signals on a control bus (18). Means are also provided feed a signal from a comparator or differential amplifier via an interrogation bus (19) to a control unit (20). Independent claims also cover a self calibration method.

公开(公告)号：DE10207315B4

公开(公告)日：2007-01-04

申请号：DE10207315

申请日：2002-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGL BERNHARD ,  GREGORIUS PETER

IPC: H04L25/04 ,  H03L7/089 ,  H03L7/091 ,  H04L7/033

Abstract: A CDR circuit arrangement, for example for a transceiver module, features a data recovery unit ( 4 ) for the recovery of the data contained in a received signal (DATA) by scanning this received data signal, and a phase evaluation unit for the determination of a suitable phase position for the scanning carried out by the data recovery unit ( 4 ). The phase evaluation unit comprises a scanning device ( 1 ) for the oversampling of a the received data signal (DATA) in accordance with several different scanning phases (P 0 -P 6 ), a phase detector device ( 2 ) for the evaluation of the scanning values (A 0 -A 6 ) accordingly prepared by the scanning device ( 1 ), in order thereby to derive intermediate signals (UP 1 -UP 3, DN 1 -DN 3 ), which classify the phase error during the scanning of the data signal by the scanning device ( 1 ) in respect of its size and direction of deviation, as well as a filter device ( 3 ), in order to subject the intermediate signals (UP 1 -UP 3, DN 1 -DN 3 ) generated by the phase detector device ( 2 ) to a weighted filtering process. In this situation, a setting signal (DeltaP) is generated by the filter device ( 3 ) for the subsequent regulation and control of the scanning phases (P 0 -P 6 ) of the scanning device ( 1 ).