公开(公告)号：JP2006318480A

公开(公告)日：2006-11-24

申请号：JP2006135151

申请日：2006-05-15

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： WALLNER PAUL ,  SCHLEDZ RALF ,  GREGORIUS PETER ,  RUCKERBAUER HERMANN

IPC: G06F12/06 ,  G06F12/00

CPC classification number: G11C5/063

Abstract: PROBLEM TO BE SOLVED: To reduce an entire power consumption as much as possible. SOLUTION: A memory system and method is disclosed. In one embodiment, a memory system has a memory controller and at least one memory module, and the fixed number of semiconductor memory chips and connection lines are disposed in specific connection forms respectively on the memory module. The connection lines have first connection lines. The first connection lines form transmission channels for transmitting data and instruction signal streams on the basis of protocols, from the memory controller to at least one memory chip on the memory module and from memory chips to the memory controller. Second connection lines are independently wired from the memory controller to at least one memory chip on the memory module, for the purpose of directly transmitting selection information to at least one memory chip separately from data and instruction signal streams. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：尽可能减少整体功耗。 解决方案：公开了一种存储器系统和方法。 在一个实施例中，存储器系统具有存储器控制器和至少一个存储器模块，并且固定数量的半导体存储器芯片和连接线分别以特定连接形式设置在存储器模块上。 连接线具有第一连接线。 第一连接线形成用于基于协议从存储器控制器到存储器模块上的至少一个存储器芯片以及从存储器芯片到存储器控制器的传输数据和指令信号流的传输通道。 第二连接线从存储器控制器独立地连接到存储器模块上的至少一个存储器芯片，用于与数据和指令信号流分离地直接将选择信息发送到至少一个存储器芯片。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO03019889A2

公开(公告)日：2003-03-06

申请号：PCT/EP0208294

申请日：2002-07-25

Applicant: INFINEON TECHNOLOGIES AG ,  GAZSI LAJOS ,  GREGORIUS PETER

Inventor： GAZSI LAJOS ,  GREGORIUS PETER

IPC: H03M1/18 ,  H04B3/14 ,  H04L25/08 ,  H04L25/03

CPC classification number: H04L25/08 ,  H03M1/185 ,  H04B3/145

Abstract: The aim of the invention is to restore data transmitted via a transmission line, especially a cable. To this end, the corresponding signal received by the receiver is amplified, and the amplified signal is then discretised by means of an analog-digital converter (6) in order to obtain a corresponding digital signal. The amplified signal is then sampled at a relatively low scanning rate, said scanning rate being in the Nyquist frequency range, or even lower than the same. The signal which is discretised in the above manner is then filtered by means of a digital high pass filter (8) and is equalised by means of a digital cable approximation filter (9) in order to compensate the distortion occurring during the transmission via the transmission line. A regenerated clock pulse is obtained from the digital signal processed in this way, by means of a phase-locked loop (14, 18), and the originally transmitted data (DATA) is recovered synchronously with said clock pulse.

Abstract translation: 对于通过传输路径重构，诸如电缆，所发送的数据，从接收信号接收到相应的信号首先被放大，然后与模拟/数字转换器（6）的帮助下，离散，以获得相应的数字信号，为此目的，将放大 具有相对低的采样率，这是在奈奎斯特频率的范围内，或者甚至可以更小大于奈奎斯特频率扫描信号。 随后，以这种方式信号的离散化过滤使用数字高通滤波器（8）和整流由数字电缆近似滤波器（9）的装置，以补偿通过所述传输链路的传输过程中发生的失真。 对于这种如此加工的数字信号的再生时钟（CLK）和同步于该时钟，原始发送的数据（DATA）被回收用锁相环（14，18）的帮助下。

公开(公告)号：WO03013084A3

公开(公告)日：2003-09-25

申请号：PCT/EP0208292

申请日：2002-07-25

Applicant: INFINEON TECHNOLOGIES AG ,  GREGORIUS PETER ,  HANNEBERG ARMIN ,  LAASER PETER

Inventor： GREGORIUS PETER ,  HANNEBERG ARMIN ,  LAASER PETER

IPC: H04L25/02

CPC classification number: H04L25/028 ,  H04L25/0272 ,  H04L25/0292

Abstract: The invention relates to a line driver (3) for conducting data transmissions with high bit rates, particularly for conducting wire-bound data transmissions in the full-duplex method. The line driver comprises a differential pair with differential pair transistors (14, 15) for generating transmit pulses according to the data to be transmitted, whereby the transmit pulses are output to the data transmission line (8, 9), which is connected to the line driver (3), preferably via cascode transistors (16, 17) that respectively form a cascode circuit with the differential pair transistors (14, 15). In order to simulate the behavior of the differential pair, a replica differential pair is provided with replica differential pair transistors (18, 19) that generate replica pulses, which correspond to transmit pulses and which can be fed via replica cascode transistors (20, 21) to a hybrid circuit (6) for carrying out echo compensation with regard to pulses received over the data transmission line (8, 9).

Abstract translation: 甲线驱动器（3），用于以高比特率的数据传输，特别是用于在全双工模式有线数据通信，包括：差动对与差动对晶体管（14，15），用于响应于该数据产生发送脉冲将被发送，其中，所述发送脉冲，优选地 通过级联晶体管（16，17），其形成所述差分对晶体管（14，15）的每一个包括一个共源共栅电路，连接到所述线驱动器（3）的数据传输线（8,9）被输出。 用于模拟差分对，副本差动对与复制品差动对晶体管的行为（18，19）被提供，其产生超过Replikkaskodentransistoren相应的副本的脉冲（20，21）的混合电路（6）的传输脉冲，以便在数据传输线方面进行回波消除 （8,9）可以提供接收脉冲。

公开(公告)号：WO02096050A3

公开(公告)日：2003-06-12

申请号：PCT/EP0205355

申请日：2002-05-15

Applicant: INFINEON TECHNOLOGIES AG ,  GREGORIUS PETER ,  HANNEBERG ARMIN

Inventor： GREGORIUS PETER ,  HANNEBERG ARMIN

IPC: H04L25/08 ,  H04L25/20

CPC classification number: H04L25/0266 ,  H04L25/085

Abstract: The invention relates to a transmitter for transmitting digital data over a transmission line (10). Said transmitter comprises a current-generating digital/analog converter (1) connected to the input of the transmitter, a current-controlled shaping filter (2) for shaping the current pulses delivered by the digital-analog converter, a line driver (5) which carries out a current-voltage conversion and an offset compensation circuit (6) arranged in a feedback path (11). In order to improve the quality of the pulses transmitted to the output of the transmitter, the internal signal processing in the transmitter is carried out based on current.

Abstract translation: 本发明涉及一种发射机用于通过传输线（10）传送数字数据，其包括一个电流驱动数字/模拟转换器（1）在发射机的输入端，一个电流动作形式的过滤器（2），用于形成由所述数字/模拟转换器提供的电流脉冲; 其执行电流/电压转换线路驱动器（5）; 和布置在反馈路径（11）偏移补偿（6）的电路。 为了改善所发送的脉冲中的发射器的输出的质量提出了基于进行内部信号处理的发射机的电流。

公开(公告)号：WO02093852A2

公开(公告)日：2002-11-21

申请号：PCT/EP0205106

申请日：2002-05-08

Applicant: INFINEON TECHNOLOGIES AG ,  DUDA THOMAS ,  GAZSI LAJOS ,  GREGORIUS PETER ,  HINZ TORSTEN ,  RENNER MARTIN

Inventor： DUDA THOMAS ,  GAZSI LAJOS ,  GREGORIUS PETER ,  HINZ TORSTEN ,  RENNER MARTIN

IPC: H04B1/10 ,  H04L7/00 ,  H04L25/00 ,  H04L25/02 ,  H04L25/04

CPC classification number: H04L25/03885

Abstract: The invention relates to a method and a device for reconstructing data pulsed with a symbol rate from a signal which was distorted as a result of transmission over a transmission link, wherein the inventive method or the device is preponderantly carried out by means of digital circuit technology or consists of said technology and is designed to improve the quality of data retrieval. The inventive method involves amplifying the signal amplitude attenuated by the transmission; filtering high frequency noise frequencies above the symbol rate; discretizing the analog signal by means of an analog/digital converter (3); executing cable approximation by means of a digitally configured cable approximation filter (7) in order to obtain an equalized signal and recovering the data from the equalized signal using a phase locking loop (20).

Abstract translation: 本发明涉及一种方法和用于在从一个信号，该信号已经在传输链路失真由传输的符号率的数据，其特征在于，本发明的方法和装置主要由数字电路技术来执行，并且由实现时钟重建的装置 提高数据恢复的质量。 本发明的方法包括扩增的由发送信号振幅衰减; 过滤高频干扰的频率的码元速率的上方; 离散模拟的模拟信号的装置/数字转换器（3）; 由数字方式实现Kabelapproximationsfilters的装置执行Kabelapproximation（7），以获得均衡后的信号; 和通过相位的手段回收来自经均衡的信号中的数据的锁相环（20）。

公开(公告)号：DE102006017767A1

公开(公告)日：2007-10-18

申请号：DE102006017767

申请日：2006-04-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WALLNER PAUL ,  GREGORIUS PETER

IPC: G11C7/10 ,  G06F12/00 ,  G11C7/22

Abstract: The chip (100) has a memory cell array (103) for reading of data, and an input circuit (102) for supplying of control signal for the memory cell array depending on externally received command data. An output buffer (107) is provided for buffering the data that are read from the memory cell array. A timer (104) is designed to control the output buffer so that the output buffer releases the buffered data in an adjustable time interval after supply of the control signal. Independent claims are also included for the following: (1) a memory controller for operating two integrated memory chip (2) a method for operating two integrated memory chip (3) a method for operating a memory controller.

公开(公告)号：DE102004014695B4

公开(公告)日：2007-08-16

申请号：DE102004014695

申请日：2004-03-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  PENTCHEV PETYO

IPC: H04L7/02 ,  H03L7/07 ,  H03L7/081 ,  H04L7/00 ,  H04L7/033

Abstract: The unit (1) has phase adjustment unit to adjust a sampling time in a center of a received data bit stream. The adjustment unit has a binary phase detection unit for detecting an average phase difference between the stream and a rotated reference phase signal. A data recognition unit has a comparator unit to compare summed up data samples with a threshold value to detect a logic value of a data bit within the stream. An independent claim is also included for a method for clock and data recovery of a received serial data bit stream.

公开(公告)号：DE10157437B4

公开(公告)日：2007-04-26

申请号：DE10157437

申请日：2001-11-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGL BERNHARD ,  GREGORIUS PETER

IPC: H04L7/033 ,  H03L7/07 ,  H03L7/091 ,  H03L7/099 ,  H04L7/02 ,  H04L25/20

Abstract: The arrangement has a commutator (1) for oversampling the received signal (S) so that several sample values of a bit cell transmitted with the signal are distributed successively to several output ports and output as intermediate signals, two stages (5,6) for combining first and second groups of intermediate signals to form data and clock recovery signals and a phase regulator (7,8) for setting sampling phases for oversampling the received signal.

公开(公告)号：DE102004052612A1

公开(公告)日：2006-05-04

申请号：DE102004052612

申请日：2004-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  GREGORIUS PETER ,  SICHERT CHRISTIAN ,  WALLNER PAUL

IPC: G11C7/10 ,  G06F11/14 ,  G11C11/4093

Abstract: A semiconductor memory module includes a plurality of semiconductor memory chips. Each semiconductor memory chip includes an interface circuit that is configured to detect a transmission error in a write datum and is further configured to output, via a separate signal path, a repeat request signal for the repeated transmission of the write datum detected as erroneous. This repeat request signal can be transmitted either as a single-bit signal or as a multibit signal (e.g., serially as an individual signal line to a superordinate memory controller).

公开(公告)号：DE102005042427A1

公开(公告)日：2006-04-13

申请号：DE102005042427

申请日：2005-09-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN ,  WALLNER PAUL

IPC: G06F12/00

Abstract: One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.