4.
    发明专利
    未知

    公开(公告)号:DE10345455A1

    公开(公告)日:2005-05-04

    申请号:DE10345455

    申请日:2003-09-30

    Abstract: An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects. A central region may be free of connection elements so that electro-migration properties of the connection structure are improved and the current-carrying capacity is increased.

    7.
    发明专利
    未知

    公开(公告)号:DE10230696B4

    公开(公告)日:2005-09-22

    申请号:DE10230696

    申请日:2002-07-08

    Abstract: A method for fabricating a short channel field-effect transistor is presented. A sublithographic gate sacrificial layer is formed, as are spacers at the side walls of the gate sacrificial layer. The gate sacrificial layer is removed to form a gate recess and a gate dielectric and a control layer are formed in the gate recess. The result is a short channel field-effect transistor with minimal fluctuations in the critical dimensions in a range below 100 nanometers.

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