公开(公告)号：JP2007110098A

公开(公告)日：2007-04-26

申请号：JP2006247813

申请日：2006-09-13

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： SCHENK ANDRE ,  TEWS HELMUT

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method of which a stress is adjusted for improved performance.
SOLUTION: A gate electrode 104 is electrically insulated from a semiconductor substrate (bulk silicon substrate, SOI layer, or the like) 102. A first side wall spacer 110 is formed along the side wall of the gate electrode 104. A sacrifice side wall spacer is so formed as to adjoin the first side wall spacer 110. The sacrifice side wall spacer and the first side wall spacer 110 cover the semiconductor substrate 102. A flattened layer is formed to cover the semiconductor substrate 102 so that a part of the flattened layer adjoins the sacrifice side wall spacer. The sacrifice side wall spacer is removed, and a recess is formed in the semiconductor substrate 102 by etching. The recess is substantially arranged between the first side wall spacer 110 and a part of the flattened layer. A semiconductor material (SiGe, SiC, or the like) 116 is deposited in the recess.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供调整应力以提高性能的半导体器件及其制造方法。 解决方案：栅电极104与半导体衬底（体硅衬底，SOI层等）102电绝缘。沿着栅电极104的侧壁形成第一侧壁间隔物110.牺牲 侧壁间隔件形成为邻接第一侧壁间隔物110.牺牲侧壁隔离物和第一侧壁隔离物110覆盖半导体衬底102.形成平坦层以覆盖半导体衬底102，使得部分 扁平层与牺牲侧壁间隔物邻接。 除去牺牲侧壁间隔物，通过蚀刻在半导体衬底102中形成凹部。 凹部基本上布置在第一侧壁间隔件110和平坦层的一部分之间。 在凹部中沉积半导体材料（SiGe，SiC等）116。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO03090257B1

公开(公告)日：2004-03-04

申请号：PCT/DE0301205

申请日：2003-04-10

Applicant: INFINEON TECHNOLOGIES AG ,  BARTH HANS-JOACHIM ,  TEWS HELMUT

Inventor： BARTH HANS-JOACHIM ,  TEWS HELMUT

IPC: C25D5/50 ,  C25D7/12 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L21/76886

Abstract: The invention relates to a method for producing thin metal-containing layers (5C) having low electrical resistance, according to which a metal-containing initial layer (5A) having a first grain size is configured on a carrier material (2) in a first step. A locally restricted heated area (W) is then created and moved within the metal-containing initial layer (5A) in such a way that the metal-containing initial layer (5A) is recrystallized so as to create the metal-containing layer (5C) having a second grain size which is enlarged to the first grain size, whereby a metal-containing layer having improved electrical properties is obtained.

Abstract translation: 本发明涉及一种用于制造含有金属的薄层（5C）具有低的电阻，其特征在于，最初具有在载体材料（2）的第一粒度前体层（5A）含金属的形成的方法。 随后，以这样的方式产生在含有金属的起始层（5A）局部限制热范围（W）和移动，使得用于制备含有金属的层（5C）的含金属的输出层（5A）的再结晶具有增加至所述第一粒度的第二粒度进行。 以这种方式，具有改善的电特性的含金属层。

公开(公告)号：WO0041459A3

公开(公告)日：2001-05-10

申请号：PCT/DE0000047

申请日：2000-01-05

Applicant: INFINEON TECHNOLOGIES AG ,  SCHREMS MARTIN ,  DRESCHER DIRK ,  WURZER HELMUT ,  TEWS HELMUT

Inventor： SCHREMS MARTIN ,  DRESCHER DIRK ,  WURZER HELMUT ,  TEWS HELMUT

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518

Abstract: The invention relates to a semiconductor element with at least one layer of tungsten oxide (WOx), optionally in a structured tungsten oxide (WOx) layer. The inventive semiconductor element is characterized in that the relative permittivity ( epsilon r) of the tungsten oxide layer (WOx) is higher than 50.

Abstract translation: 根据本发明，具有至少一个氧化钨的层（的WOx），半导体装置任选地提供氧化钨（WO x）的图形层。 本发明的半导体装置的特征在于，所述氧化钨（WO x）的相对介电常数（ε-r）为低于50更大

公开(公告)号：WO2005038930A2

公开(公告)日：2005-04-28

申请号：PCT/EP2004052333

申请日：2004-09-28

Applicant: INFINEON TECHNOLOGIES AG ,  TEWS HELMUT ,  FEHLHABER RODGER

Inventor： TEWS HELMUT ,  FEHLHABER RODGER

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  B81C1/00

CPC classification number: H01L29/7851 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795

Abstract: Disclosed is a structuring method, among other things. According to said method, a filling material (22) having a T-shaped cross section is used as a structuring mask in order to create structures with sublithographic dimensions, particularly a double-fin field effect transistor.

Abstract translation: 其中特别说明了一种图案化方法，其中使用T形横截面的填充材料（22）作为构图掩模以产生具有亚光刻尺寸的结构，特别是双鳍场效应晶体管。

公开(公告)号：WO2005038922A2

公开(公告)日：2005-04-28

申请号：PCT/EP2004052216

申请日：2004-09-16

Applicant: INFINEON TECHNOLOGIES AG ,  TEWS HELMUT

Inventor： TEWS HELMUT

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10841 ,  H01L27/1082 ,  H01L27/10823 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/161 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827 ,  Y10T29/41

Abstract: Disclosed is a field effect transistor (37), among other things, which comprises a monocrystalline control area (34). The inventive field effect transistor (37) provides a certain degree of freedom concerning the circuitry design and can be produced in a simple manner.

Abstract translation: 进行了说明，除其他外，一个场效应晶体管（37）具有单晶控制部（34）。 所述场效应晶体管（37），用于电路设计提供了自由和能够容易地制造。

公开(公告)号：WO0237561A2

公开(公告)日：2002-05-10

申请号：PCT/US0143859

申请日：2001-11-06

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： TEWS HELMUT ,  WEYBRIGHT MARY ,  KUDELKA STEPHAN ,  GLUSCHENKOV OLEG ,  HEGDE SURI

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/518 ,  Y10S438/981

Abstract: A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising:a) growing a sacrificial oxide layer on a substrate;b) implanting a dopant through the sacrificial oxide layer;c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface;e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide;f) implanting a second dosage of nitrogen ions through the photoresist;g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.

Abstract translation: 一种用于形成用于高性能DRAM系统或逻辑电路的改进的氧化物厚度均匀性的双栅极氧化物的方法，包括：a）在衬底上生长牺牲氧化物层; b）通过所述牺牲氧化物层注入掺杂剂; c） 不存在光致抗蚀剂的氮离子的第一剂量形成氮化硅层; d）对衬底进行快速热退火足够的时间和足够的温度以使氮气扩散到硅/氧化物界面; e）用光致抗蚀剂掩蔽衬底以限定双重氧化物的薄氧化物的位置 栅极氧化物; f）通过光致抗蚀剂注入第二剂量的氮离子; g）剥离光致抗蚀剂和牺牲氧化物层; 和h）通过氧化栅氧化层生长，其特征在于在薄和厚的氧化物中的氮离子注入区域中改善的氧化物厚度均匀性。

公开(公告)号：WO2006076991A3

公开(公告)日：2006-10-26

申请号：PCT/EP2005056641

申请日：2005-12-09

Applicant: INFINEON TECHNOLOGIES AG ,  KAKOSCHKE RONALD ,  TEWS HELMUT

Inventor： KAKOSCHKE RONALD ,  TEWS HELMUT

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/2815 ,  H01L27/088 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/7311 ,  H01L29/78 ,  H01L29/7835

Abstract: The invention inter alia relates to a method for producing a tunnel field-effect transistor (T1). The inventive method is characterized by producing differently doped connecting areas (28, 80) by means of self-aligned implantation methods.

Abstract translation: 其中，说明用于制造隧道场效应晶体管（T1）的方法。 通过自对准注入技术产生不同掺杂类型的端子区（28,80）。

公开(公告)号：WO2004057660A2

公开(公告)日：2004-07-08

申请号：PCT/DE0304046

申请日：2003-12-09

Applicant: INFINEON TECHNOLOGIES AG ,  TEWS HELMUT ,  FEHLHABER RODGER

Inventor： TEWS HELMUT ,  FEHLHABER RODGER

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/336

CPC classification number: H01L21/2815 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/84

Abstract: The invention relates to a method for producing: a sublithographic gate structure; an associated field effect transistor; an associated inverter, and; an associated inverter structure. A sublithographic gate structure (SG) having slight variations in the critical dimensions thereof can be directly produced on the lateral walls of a lithographically structured mask (M0, 2) by the conformal formation of a gate insulation layer (3) and of a gate layer with subsequently executed anisotropic etching.

Abstract translation: 本发明涉及一种用于制造亚光刻栅极结构，相关联的场效应晶体管和相关联的逆变器以及相关联的逆变器结构的，具有光刻图案化掩模的侧壁（M0，2）保形形成栅极绝缘层（3）和栅极层 已执行以下各向异性蚀刻（SG）可以在直接的临界尺寸亚光刻栅极结构的小变化来制造。

公开(公告)号：WO03090257A2

公开(公告)日：2003-10-30

申请号：PCT/DE0301205

申请日：2003-04-10

Applicant: INFINEON TECHNOLOGIES AG ,  BARTH HANS-JOACHIM ,  TEWS HELMUT

Inventor： BARTH HANS-JOACHIM ,  TEWS HELMUT

IPC: C25D5/50 ,  C25D7/12 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/76886

Abstract: The invention relates to a method for producing thin metal-containing layers (5C) having low electrical resistance, according to which a metal-containing initial layer (5A) having a first grain size is configured on a carrier material (2) in a first step. A locally restricted heated area (W) is then created and moved within the metal-containing initial layer (5A) in such a way that the metal-containing initial layer (5A) is recrystallized so as to create the metal-containing layer (5C) having a second grain size which is enlarged to the first grain size, whereby a metal-containing layer having improved electrical properties is obtained.

Abstract translation: 本发明涉及一种用于制造含有金属的薄层（5C）具有低的电阻，其特征在于，最初具有在载体材料（2）的第一粒度前体层（5A）含金属的形成的方法。 随后，以这样的方式产生在含有金属的起始层（5A）局部限制热范围（W）和移动，使得用于制备含有金属的层（5C）的含金属的输出层（5A）的再结晶具有增加至所述第一粒度的第二粒度进行。 以这种方式，得到具有改善的电性能的含金属层。

公开(公告)号：DE102009001522A1

公开(公告)日：2011-08-04

申请号：DE102009001522

申请日：2009-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  TEWS HELMUT

IPC: H01L25/16 ,  H01L21/58 ,  H01L21/60 ,  H01L27/06 ,  H01L29/92

Abstract: Ein Ausführungsbeispiel der Erfindung ist eine Halbleiterstruktur 110 mit einem Halbleiterchip 200, der zumindest teilweise in einer Trägervorrichtung 410 eingebettet ist; und einem Kondensator 300, der außerhalb der lateralen Begrenzung des Chips 200 angeordnet ist, wobei der Kondensator 300 elektrisch an den Chip 200 gekoppelt ist.