1.
    发明专利
    未知

    公开(公告)号:DE19962677A1

    公开(公告)日:2001-07-05

    申请号:DE19962677

    申请日:1999-12-23

    Abstract: The configuration allows for testing a multiplicity of semiconductor chips with respect to critical parameters on the wafer level. Each of the semiconductor chips on a semiconductor wafer is additionally provided with at least one option pad. The option pad allows access for a test program to the chip for separating out the semiconductor chips which do not correspond to predetermined requirements for critical parameters.

    2.
    发明专利
    未知

    公开(公告)号:DE19946495C2

    公开(公告)日:2002-10-24

    申请号:DE19946495

    申请日:1999-09-28

    Abstract: The measuring pad reduction arrangement uses an A/D converter (3) within the IC chip (1) for providing digital internal voltage values supplied via an input/output pad (9) to an external fuse cutter (5), for cutting fuses (7) within the IC chip. The internal voltages are supplied to the A/D converter from different points within the integrated circuit, the external fuse cutter having a processor (6) comparing the internal voltage values with required values for selective cutting of the fuses.

    3.
    发明专利
    未知

    公开(公告)号:DE19946495A1

    公开(公告)日:2001-04-19

    申请号:DE19946495

    申请日:1999-09-28

    Abstract: The measuring pad reduction arrangement uses an A/D converter (3) within the IC chip (1) for providing digital internal voltage values supplied via an input/output pad (9) to an external fuse cutter (5), for cutting fuses (7) within the IC chip. The internal voltages are supplied to the A/D converter from different points within the integrated circuit, the external fuse cutter having a processor (6) comparing the internal voltage values with required values for selective cutting of the fuses.

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