公开(公告)号：JP2001237285A

公开(公告)日：2001-08-31

申请号：JP2000385881

申请日：2000-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROBERT FOIRURE ,  SAVIGNAC DOMINIQUE

IPC: G01R31/28 ,  G01R31/3185 ,  G11C11/401 ,  G11C29/56 ,  H01L21/66 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To determine if semiconductor chips satisfy requirements or not by providing a device for testing a large number of the semiconductor chips to inspect a variety of timing parameters of the semiconductor chips on a wafer surface. SOLUTION: The device for testing a number of the semiconductor chips is configured with the following characteristics. Each of the semiconductor chips on the semiconductor wafer has at least one option pad. A test program is supplied to the semiconductor chips via the pads on the wafer surface. Thus, the semiconductor chips not satisfying the predetermined requirements for the critical parameters are removed.

公开(公告)号：JP2000252439A

公开(公告)日：2000-09-14

申请号：JP2000045945

申请日：2000-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRYSOSTOMIDES ATHANASIA ,  FEURLE ROBERT ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: H01L21/8242 ,  G11C7/06 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To avoid a critical diffusion region interval between sense amplifier transistor groups for optimum combination with a sense amplifier transistor by arranging a driver for the sense amplifier transistor parallel to a diffusion region while directly adjacent to it. SOLUTION: For a transistor 6 of each conductive type, one diffusion region 8 extending as band is provided, respectively. For the diffusion region 8 for the sense amplifier transistor 6, one driver 5 is provided parallel to it, respectively. Thus, a critical diffusion region interval is avoided at completion. An optimum combination between the driver 5 and the sense amplifier transistor 6 is possible, with no such large wiring resistance as to delay an electric-charge transfer. Thus, an optimum combination to the driver 5 of the sense amplifier transistor is performed with no large wiring resistance accompanied, allowing a perfect molten structure of the diffusion region 8 of the sense amplifier transistor 6.

公开(公告)号：JP2002198442A

公开(公告)日：2002-07-12

申请号：JP2001340062

申请日：2001-11-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  KAISER ROBERT ,  PFEFFERL KARL-PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: G11C11/401 ,  G11C5/02 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/50 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a memory block having a flexible structure. SOLUTION: The memory structure has a contact block (1), and cell blocks (2-9) adjacent to the contact block (1). The contact block (1) is located in the center, the cell blocks (2-9) abut on the four sides of the contact block (1), respectively, and the cell blocks (2-9) are arranged annularly around the contact block (1). The cell block (2) has two sides abutting, respectively, on two other cell blocks (3, 9) and the cell blocks (2-9) are divided into first and second sub-cell blocks (21, 22) in the longitudinal direction.

公开(公告)号：JP2002175690A

公开(公告)日：2002-06-21

申请号：JP2001279684

申请日：2001-09-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROBERT FOIRURE ,  SAVIGNAC DOMINIQUE

IPC: G11C11/401 ,  G11C11/34 ,  G11C11/407 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide an integrated memory which has memory cells and buffer capacitors in plane state arrangement being sufficiently uniform and in which comparatively high voltage tolerance can be made continuously by these buffer capacitors. SOLUTION: In this memory, each memory cell has a selective transistor and a memory capacitor, the memory capacitor is connected to one of a plurality of column lines through the selective transistor for each memory cell, a control terminal of the selective transistor is connected to one of row lines for each memory cell, each buffer capacitor is connected to another column line by a contact, and the buffer capacitor is provided so that a connection path between each buffer capacitor and contact is arranged in parallel to another row line.

公开(公告)号：JP2000252438A

公开(公告)日：2000-09-14

申请号：JP2000043268

申请日：2000-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRYSOSTOMIDES ATHANASIA ,  FEURLE ROBERT ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor storage device wherein components are little affected by neighborhood action at manufacturing, providing connected diffusion regions. SOLUTION: Provided on a vacant surface 4, a dummy component 3 is identical with a component adjacent to a memory cell field or similar, as possible, to the component, while provided in the connected diffusion regions 5 common to the component adjacent to the dummy component.

公开(公告)号：DE102012213101B4

公开(公告)日：2019-10-10

申请号：DE102012213101

申请日：2012-07-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ALLERS WOLF ,  NIRSCHL THOMAS ,  OTTERSTEDT JAN ,  SAVIGNAC DOMINIQUE

IPC: G11C16/06 ,  H01L27/115

Abstract: Ein Speicher (100), der folgende Merkmale aufweist:eine Speicherzelle (102), die einen ersten Anschluss (110), einen zweiten Anschluss (112) und einen Kanal (114) aufweist, der sich zwischen dem ersten Anschluss (110) und dem zweiten Anschluss (112) erstreckt;ein Energiespeicherungselement (104), das ausgebildet ist, eine Programmierung der Speicherzelle (102) zu unterstützen, wobei das Energiespeicherungselement (104) mit dem ersten Anschluss (110) gekoppelt ist;eine Energiezufuhreinrichtung (116), die mit dem Energiespeicherungselement (104) gekoppelt ist; undeine Steuerung (108), die ausgebildet ist, die Energiezufuhreinrichtung (106) zu aktivieren und den Kanal (114) der Speicherzelle (102) in einen nicht leitfähigen Zustand zu bringen, zum Versorgen des Energiespeicherungselements (104) mit Energie, und um nachfolgend den Kanal (114) der Speicherzelle (102) in einen leitfähigen Zustand zu bringen, wobei die Speicherzelle (102) ein Auswahlgate (202) aufweist; undwobei die Steuerung ausgebildet ist, ein Signal an dem Auswahlgate (202) von einem ersten Signalpegel auf einen zweiten Signalpegel rampenförmig einzustellen, um den Kanal in den leitfähigen Zustand zu bringen, zum Programmieren der Speicherzelle (102) bei Erreichen der Schwellenspannung der Speicherzelle (102) während des rampenförmigen Einstellens des Signalpegels basierend auf der Energie, die in dem Energiespeicherungselement (104) gespeichert ist.

公开(公告)号：DE102005001590B4

公开(公告)日：2007-08-16

申请号：DE102005001590

申请日：2005-01-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  BENDER CARSTEN ,  GRAFE JUERGEN ,  WENNEMUTH INGO ,  GOSPODINOVA MINKA ,  SAVIGNAC DOMINIQUE

IPC: H01L23/50 ,  H01L25/065

公开(公告)号：DE102004055046A1

公开(公告)日：2006-05-24

申请号：DE102004055046

申请日：2004-11-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  SICHERT CHRISTIAN ,  SAVIGNAC DOMINIQUE ,  GREGORIUS PETER ,  WALLNER PAUL

IPC: G11C7/00 ,  G11C11/407

Abstract: A semiconductor memory system has data transmission lines (DQ) connecting the interface circuits (1-4;5a, 5b) and via which the signal bursts of the write and read data signals of given burst lengths are transmitted from and to the memory control unit (20) and from and to the register unit (15a). The interface circuits are set up for transmission of the burst lengths at least of the write data expanded additional bits (ZB) together with at least each n-th signal burst. An independent claim is included for a method for transmission of write- read- data signals.

公开(公告)号：DE10123594B4

公开(公告)日：2006-04-20

申请号：DE10123594

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE

IPC: H01L27/085 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108

Abstract: It is known to adapt the dimensions of transistors, in particular a layer thickness of a local gate oxide in a manner dependent on an operating voltage. Therefore, semiconductor circuits having transistors with different operating voltages are provided with transistors having gate oxides of different thicknesses. This allows the gate oxide thickness to be influenced even more extensively. In this case, account is taken of the fact that infrequently addressed transistors, in particular memory transistors given the same gate oxide thickness, have a significantly longer lifetime than frequently switched transistors. An integrated semiconductor circuit having transistors whose gate oxide thicknesses are adapted to the switching frequency having different magnitudes, is proposed.

公开(公告)号：DE10126130A1

公开(公告)日：2002-12-12

申请号：DE10126130

申请日：2001-05-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUCH LOTHAR ,  GRUENING-VON SCHWERIN ULRICKE ,  HAFFNER HENNING ,  KOWALEWSKI JOHANNES ,  SAVIGNAC DOMINIQUE ,  MORHARD KLAUS-DIETER ,  THIELSCHER GUIDO ,  TRINOWITZ REINER

IPC: G03F1/00 ,  H01L21/768 ,  H01L21/28

Abstract: The method involves using a mask illuminated with short-wave light in an optical lithographic method. The mask has elongated, slit-shaped openings for producing essentially circular and/or elongated contact holes (2,6). The illumination conditions are selected so that an image reduction of at least 200 to 400 nm. occurs in the longitudinal direction of the openings.