公开(公告)号：DE102005050811B3

公开(公告)日：2007-02-15

申请号：DE102005050811

申请日：2005-10-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZIMMERMANN ULRICH ,  GERBER RALF

IPC: G11C7/12

Abstract: The device has memory cells (2) with a selection transistor, where gates of the transistor are connected to word lines. A pair of bit lines is connected to a sense amplifier, and two memory cells (6) are connected to the bit lines. A control switching device (7`) is provided, where gates of the memory cells (6) are switchable by the device (7`) at the beginning of a preloading process for loading the bit lines to a compensation voltage. An independent claim is also included for a method for increasing readability of a dynamic random access memory-memory cell in a memory cell field.

公开(公告)号：DE102005034387A1

公开(公告)日：2007-02-08

申请号：DE102005034387

申请日：2005-07-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GERBER RALF ,  ZIMMERMANN ULRICH

IPC: H01L27/108 ,  H01L21/8242

Abstract: A trench DRAM semiconductor memory comprises a cell field (1) with parallel strips (2) of memory cells mutually insulated by shallow trench isolation (19) with neighboring cells along a strip also mutually isolated. A p-trench zone (11) in a semiconductor body (10) has an n-channel transistor per cell with source/drain connections to a bitline and through a buried strip to an electrode of a trench memory capacitor. A p-type anti-punch zone (23') lies in the trench beneath the bitline. An independent claim is also included for the production of an anti-punch zone for the above.

公开(公告)号：DE102005000841B4

公开(公告)日：2007-04-05

申请号：DE102005000841

申请日：2005-01-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GERBER RALF

IPC: G11C7/06 ,  G11C5/14 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4091 ,  G11C29/56

Abstract: An integrated semiconductor memory device includes memory cells which are connected to first sense amplifiers or second sense amplifiers via in each case one bit line pair. During a read access of one of the memory cells, the sense amplifier connected to the memory cell to be read out evaluates a cell voltage of the memory cell to be read out and generates a data item with a logical Low or High level depending on the level of the cell voltage at a data terminal. However, if the sense amplifiers are not of identical construction or arrangement, the same cell voltage level is evaluated differently by the first sense amplifier than by the sense amplifier. To match the evaluation performance of the first and second sense amplifiers, the connected bit line pairs are precharged to different precharging voltages before a read access.

公开(公告)号：DE102005000841A1

公开(公告)日：2006-07-13

申请号：DE102005000841

申请日：2005-01-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GERBER RALF

IPC: G11C7/06 ,  G11C5/14 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4091 ,  G11C29/00

Abstract: An integrated semiconductor memory device includes memory cells which are connected to first sense amplifiers or second sense amplifiers via in each case one bit line pair. During a read access of one of the memory cells, the sense amplifier connected to the memory cell to be read out evaluates a cell voltage of the memory cell to be read out and generates a data item with a logical Low or High level depending on the level of the cell voltage at a data terminal. However, if the sense amplifiers are not of identical construction or arrangement, the same cell voltage level is evaluated differently by the first sense amplifier than by the sense amplifier. To match the evaluation performance of the first and second sense amplifiers, the connected bit line pairs are precharged to different precharging voltages before a read access.