公开(公告)号：DE59914831D1

公开(公告)日：2008-09-25

申请号：DE59914831

申请日：1999-03-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUSCH ANDREAS ,  ROTHENHAEUSSER STEFFEN ,  TRUEBY ALEXANDER ,  OTANI YOICHI ,  ZIMMERMANN ULRICH

IPC: H01L27/112 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10

Abstract: A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.

公开(公告)号：DE102005050811B3

公开(公告)日：2007-02-15

申请号：DE102005050811

申请日：2005-10-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZIMMERMANN ULRICH ,  GERBER RALF

IPC: G11C7/12

Abstract: The device has memory cells (2) with a selection transistor, where gates of the transistor are connected to word lines. A pair of bit lines is connected to a sense amplifier, and two memory cells (6) are connected to the bit lines. A control switching device (7`) is provided, where gates of the memory cells (6) are switchable by the device (7`) at the beginning of a preloading process for loading the bit lines to a compensation voltage. An independent claim is also included for a method for increasing readability of a dynamic random access memory-memory cell in a memory cell field.

公开(公告)号：DE102004048745A1

公开(公告)日：2006-04-13

申请号：DE102004048745

申请日：2004-10-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZIMMERMANN ULRICH

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/108

Abstract: Bit conducting structure consists of a number of parallel bit conductors in a storage element. The bit conductors are formed in two sets (A,B) as primary (22A) and secondary (22B) conductors, on different horizontal levels. The second set of conductors is on a higher plane than the first set. Adjacent bit conductors are on different horizontal planes.

公开(公告)号：DE102005060086A1

公开(公告)日：2007-06-21

申请号：DE102005060086

申请日：2005-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZIMMERMANN ULRICH

IPC: G11C29/50

Abstract: The method involves connecting a storage cell (122a) to a ring oscillator (110). Frequencies that are resulting from the oscillator are measured. An access transistor (122) is inserted in a conductive state for connecting the cell to the oscillator. The cell is separated from the oscillator, and the frequencies of the oscillator after separating from the cell are measured. The frequencies of the oscillator connected with the cell are compared with the frequencies of the oscillator after separated from the cell : An independent claim is also included for a semiconductor memory comprising a storage cell.

公开(公告)号：DE102005034387A1

公开(公告)日：2007-02-08

申请号：DE102005034387

申请日：2005-07-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GERBER RALF ,  ZIMMERMANN ULRICH

IPC: H01L27/108 ,  H01L21/8242

Abstract: A trench DRAM semiconductor memory comprises a cell field (1) with parallel strips (2) of memory cells mutually insulated by shallow trench isolation (19) with neighboring cells along a strip also mutually isolated. A p-trench zone (11) in a semiconductor body (10) has an n-channel transistor per cell with source/drain connections to a bitline and through a buried strip to an electrode of a trench memory capacitor. A p-type anti-punch zone (23') lies in the trench beneath the bitline. An independent claim is also included for the production of an anti-punch zone for the above.

公开(公告)号：DE10310811A1

公开(公告)日：2004-09-30

申请号：DE10310811

申请日：2003-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZIMMERMANN ULRICH ,  MOLL HANS-PETER

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: Production of a trench capacitor comprises forming a trench (5) in a substrate (1) using a hard mask (2, 3), forming a capacitor dielectric (30) in the lower and middle trench region, an insulating collar (10) in the middle and upper region and an electrically conducting filler (20) in the trench, forming a mask on the resulting structure to expose a part of the filler and the collar in the trench, removing the exposed part of the collar to expose a connecting region (KS) of a trenches contact, removing the mask, and filling the exposed connecting region with a further electrically conducting filler (22).

公开(公告)号：DE10257337A1

公开(公告)日：2003-06-26

申请号：DE10257337

申请日：2002-12-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PETTER ROBERT ,  ZIMMERMANN ULRICH

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C7/00 ,  G11C29/00

Abstract: A system and method for determining the accuracy of the states of fuses by changing, or not changing, the state of additional fuses. The system includes a memory including addressable storage elements, address fuses whereby each fuse includes a link in a connected or disconnected state and the collective state of the address fuses identifies an address value, a parity fuse whereby the fuse includes a link in a connected or disconnected state and the state of the parity fuse represents a parity value, the parity value being based on, but not equivalent to, the address of an addressable storage element, and; an output providing a value dependant upon the address value and the parity value.

公开(公告)号：DE10310811B4

公开(公告)日：2006-07-27

申请号：DE10310811

申请日：2003-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZIMMERMANN ULRICH ,  MOLL HANS-PETER

IPC: H01L21/8242 ,  H01L21/334 ,  H01L27/108

公开(公告)号：DE19630050B4

公开(公告)日：2005-03-10

申请号：DE19630050

申请日：1996-07-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZIMMERMANN ULRICH ,  HAIN MANFRED

IPC: H01L21/8246 ,  H01L21/312

公开(公告)号：DE59709112D1

公开(公告)日：2003-02-13

申请号：DE59709112

申请日：1997-08-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZIMMERMANN ULRICH

IPC: H01L21/8246 ,  H01L27/112

Abstract: A semiconductor read-only memory (ROM) has trenches and vertical transistors. The trenches are filled with insulator material during the manufacturing process. Holes, which are as wide as the trenches are etched into the insulator at regions where word lines and decoder lines are to be provided over the trenches in a later manufacturing step. In a subsequent masking process for changing the conductivity characteristic of channel regions of transistors, channel regions selected according to programming requirements, are doped. The insulator remaining in the trenches prevents that regions under the insulator material are affected by the masking method.