公开(公告)号：DE10107141A1

公开(公告)日：2002-08-29

申请号：DE10107141

申请日：2001-02-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRIMM WOLFGANG ,  SCHNEIDER HELMUT

IPC: H04L25/08 ,  H03K5/00 ,  H04B3/32

Abstract: The method involves using a coupling capacitance formed between two conducting tracks (A,B) and a first signal (PHI A) formed on the first of the two conducting tracks, whereby the electrical circuit element (1) is arranged on the second conducting track. The time variation of a second signal is accelerated by the control exerted on the circuit element. Independent claims are also included for the following: an electrical circuit with two conducting tracks and at least one circuit element.

公开(公告)号：DE10128580A1

公开(公告)日：2003-01-02

申请号：DE10128580

申请日：2001-06-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRIMM WOLFGANG

IPC: H01L27/02 ,  H01L27/092

Abstract: The circuit configuration, in particular a logic or digital circuit, has transistors of different conductivity types. The transistors are disposed in spaced-apart rows. The transistor rows alternate with regard to the conductivity types. The transistors of the rows form groups. A group of the first conductivity type is associated with a group of the second conductivity type in an adjacent row and the associated groups together form a digital functional unit. A first, second, and third transistor row each contain transistor groups with an associated group in a downstream adjacent row (in a given direction) and transistor groups with an associated group in an upstream adjacent row. The second transistor row is formed between the first and third transistor rows and contains a transistor group that is associated with a group of the first row, and a transistor group that is associated with a group of the third row.

公开(公告)号：DE10128580B4

公开(公告)日：2006-04-13

申请号：DE10128580

申请日：2001-06-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRIMM WOLFGANG

IPC: H01L27/092 ,  H01L27/02

Abstract: The circuit configuration, in particular a logic or digital circuit, has transistors of different conductivity types. The transistors are disposed in spaced-apart rows. The transistor rows alternate with regard to the conductivity types. The transistors of the rows form groups. A group of the first conductivity type is associated with a group of the second conductivity type in an adjacent row and the associated groups together form a digital functional unit. A first, second, and third transistor row each contain transistor groups with an associated group in a downstream adjacent row (in a given direction) and transistor groups with an associated group in an upstream adjacent row. The second transistor row is formed between the first and third transistor rows and contains a transistor group that is associated with a group of the first row, and a transistor group that is associated with a group of the third row.

公开(公告)号：DE10134955C1

公开(公告)日：2003-03-06

申请号：DE10134955

申请日：2001-07-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRIMM WOLFGANG

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/08 ,  H01L27/108 ,  H01L31/119

Abstract: Arrangement of trenches in a semiconductor substrate, in particular for trench capacitors The present invention provides an arrangement of trenches in a semiconductor substrate, in particular for trench capacitors, having a plurality of regularly arranged trenches (G1'-G4'; G1''-G4'') which extend in a depth direction (T) proceeding from a surface (O) of the semiconductor substrate; the trenches (G1'-G4'; G1''-G4'') having in each case an at least one widened region in the depth direction (T); and widened regions of adjacent trenches (G1'-G4'; G1''-G4'') are offset relative to one another in the depth direction.

公开(公告)号：DE102005007840A1

公开(公告)日：2006-09-07

申请号：DE102005007840

申请日：2005-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRIMM WOLFGANG

IPC: H01L23/528

Abstract: The device has a contact hole layer with a planar interface. Another interface is parallel to the former interface. A contact channel (44) is provided in the layer, where the channel comprises an angle between 0 and 90 degrees in a direction normal to the planar interfaces. Conducting paths arranged vertically are isolated from one another and paths that are not arranged vertically are connected to each other by the contact channel.