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公开(公告)号:DE102005062967A1
公开(公告)日:2006-07-13
申请号:DE102005062967
申请日:2005-12-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor: GROSS HARALD
IPC: H01L23/66
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公开(公告)号:DE102005055402A1
公开(公告)日:2007-05-31
申请号:DE102005055402
申请日:2005-11-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WALLIS DAVID , GROSS HARALD
Abstract: Forming a wiring structure on a wafer substrate connecting chip bond pads and contact pads for center-row arrangements, wafer-level packages (WLP) or known good dies (KGD) comprises sputtering a seed layer on the structure substrate surface, spinning a photoresist and applying a photolithographic structure to form a square-edged trench, galvanically applying a thin copper layer (12) on trench walls and base, removing the resist and etching the seed layer. A dielectric cover (13) is then spun on.
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公开(公告)号:DE102004039906A1
公开(公告)日:2005-08-18
申请号:DE102004039906
申请日:2004-08-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor: GROSS HARALD
IPC: H01L21/50 , H01L21/60 , H01L21/98 , H01L23/485 , H01L25/065
Abstract: Producing an electronic component with a number of integrated members, comprises forming planar integrated members (2) with a surface that contains the circuit, and an edge surface with a contact surface (6). At least two components are located on top of each other, and the contact surfaces are connected using bond wires.
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