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    METHOD FOR FORMING PROTECTIVE COATINGS ON WAFER BASE SURFACE
    1.
    发明专利
    METHOD FOR FORMING PROTECTIVE COATINGS ON WAFER BASE SURFACE 审中-公开

    公开(公告)号：JP2004006635A

    公开(公告)日：2004-01-08

    申请号：JP2003011776

    申请日：2003-01-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： VASQUEZ BARBARA ,  WALLIS DAVID ,  WINTER SYLVIA

    IPC: H01L21/301 ,  H01L21/304 ,  H01L21/68 ,  H01L21/78

    Abstract: PROBLEM TO BE SOLVED: To provide the rear processing method of a wafer to form a trench on the front surface of a wafer by sawing or etching, to grind the wafer from the base side, to fill the trench with protective materials, to coat the base front surface as the surface layer, and to harden it. SOLUTION: In this method, a trench is formed on the front surface of wafer 1 by sawing or etching, the wafer 1 is ground from the base side, the trench is filled with protective materials 8, which is also applied to the base surface as the surface layer. Then, the protective materials 8 are hardened in order to carry out the sawing process. In another embodiment of this method, double thin film layers are formed on the rear face of the wafer 1 including a mounting tape 6 and a protective layer 8 faced to the rear face of the wafer 1. COPYRIGHT: (C)2004,JPO

    3.
    发明专利
    未知

    公开(公告)号：DE102004035080A1

    公开(公告)日：2005-12-29

    申请号：DE102004035080

    申请日：2004-07-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TROVARELLI OCTAVIO ,  BRINTZINGER AXEL ,  UHLENDORF INGO ,  RUCKMICH STEFAN ,  WALLIS DAVID

    IPC: H01L23/12 ,  H01L23/522 ,  H01L23/528

    Abstract: An arrangement reduces the electrical crosstalk on a chip, in particular between adjacent conductors of the redistribution routing and/or between the redistribution routing on the first passivation on the chip and the metallization of the chip. In one aspect, the arrangement reduces the crosstalk between the redistribution wiring on a chip and its metallization and can be realized simply and independently at the front end. This is achieved by at least an additional conductor ( 10 ) being respectively arranged between adjacent conductors of the redistribution routing ( 1 ) and/or at least a second passivation ( 7 ) with a lower dielectric constant of a preferred "cold dielectric" being arranged between the redistribution routing ( 1 ) and the first passivation ( 2 ) on the active region of the chip ( 3 ).

    Making wiring circuit panel, employs structured masking layers to define through-contact locations, with selective use of protective layers when depositing conductor structures
    6.
    发明专利
    Making wiring circuit panel, employs structured masking layers to define through-contact locations, with selective use of protective layers when depositing conductor structures 未知

    公开(公告)号：DE102004050476B3

    公开(公告)日：2006-04-06

    申请号：DE102004050476

    申请日：2004-10-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TROVARELLI OCTAVIO ,  BRINTZINGER AXEL ,  UHLENDORF INGO ,  RUCKMICH STEFAN ,  WALLIS DAVID

    IPC: H01L23/50 ,  H01L21/48 ,  H05K7/20

    Abstract: Masking layers (3) are applied and structured on both sides of the substrate wafer (1), to form a first contact location (6) on the first surface (11) and a second contact location (6) on the second surface (12). A protective layer is applied to the second surface, to protect the masking and contact on that side, during the following stages. A conductor structure (7) is deposited on the first surface (11), covering the first contact location. The protective layer on the second surface is removed, and the second conductor structure (7) is applied, to cover the second contact location on the second surface (12). In a further stage, a protective layer is applied to the first surface. Application of the masking layer on the first and second surfaces comprises evaporation, immersion coating and gas phase deposition. Structuring of the masking layer is carried out by lithographic- and etching processes. The first and/or second protective layer is applied using immersion coating, spray coating or rotation coating. The first and/or second protective layers are formed from plastic film, which is adhered or laminated to the respective surface. The substrate wafer is prepared from a silicon substrate.

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