公开(公告)号：WO2005031746A3

公开(公告)日：2005-06-23

申请号：PCT/EP2004010747

申请日：2004-09-24

Applicant: INFINEON TECHNOLOGIES AG ,  ALEXANDER GEORGE WILLIAM ,  HAN JONGHEE ,  PARTSCH TORSTEN

Inventor： ALEXANDER GEORGE WILLIAM ,  HAN JONGHEE ,  PARTSCH TORSTEN

IPC: G11C7/10

CPC classification number: G11C7/1078 ,  G11C7/1087 ,  G11C7/1093

Abstract: A random access memory comprises a first circuit (130) configured to receive a strobe signal (132) and provide pulses in response to transitions in the strobe signal. The random access memory comprises a second circuit (100, 100n) configured to receive the strobe signal to latch data into the second circuit, and to receive the pulses to latch the latched data into the second circuit after the transitions in the strobe signal.

Abstract translation: 随机存取存储器包括被配置为接收选通信号（132）并响应于选通信号中的转变提供脉冲的第一电路（130）。 随机存取存储器包括被配置为接收选通信号以将数据锁存到第二电路中的第二电路（100,100n），并且在选通信号中的转换之后接收脉冲以将锁存的数据锁存到第二电路中。

公开(公告)号：DE112004001952B4

公开(公告)日：2015-08-20

申请号：DE112004001952

申请日：2004-10-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAN JONGHEE ,  KIM JUNG PILL

IPC: G11C11/406 ,  G11C5/06 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4091

Abstract: Ein Verfahren zum Rückführen einer Ladung bei einer Speichervorrichtung, das folgende Schritte aufweist: Durchführen einer ersten Auffrischoperation, die ein erstes Array von Bitleitungserfassungsverstärkern betrifft; Übertragen von Ladung von Leistungsleitungen des ersten Arrays von Bitleitungserfassungsverstärkern zu Leistungsleitungen eines zweiten Arrays von Bitleitungserfassungsverstärkern, die bei einer zweiten Auffrischoperation betroffen sind, die nachfolgend zu der ersten Auffrischoperation durchgeführt wird; und Übertragen von Ladung von Leistungsleitungen des ersten Arrays von Bitleitungserfassungsverstärkern zu Leistungsleitungen eines dritten Arrays von Bitleitungserfassungsverstärkern, die bei einer dritten Auffrischoperation betroffen sind, die nachfolgend zu der zweiten Auffrischoperation durchgeführt wird, wobei das Verfahren ferner ein Durchführen zumindest einer Zwischenauffrischoperation zwischen der ersten und der zweiten Auffrischoperation aufweist, wobei eine Ladung nicht von Leistungsleitungen des Arrays von Bitleitungserfassungsverstärkern zu Leistungsleitungen eines Arrays von Bitleitungserfassungsverstärkern übertragen wird, die bei der Zwischenauffrischoperation betroffen sind.

公开(公告)号：DE102004055679A1

公开(公告)日：2005-06-23

申请号：DE102004055679

申请日：2004-11-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAN JONGHEE

IPC: H03K19/003

Abstract: Buffer circuits and techniques that reduce skew between rising and falling times of output data as process conditions vary are provided. One or more process-dependent current sources may be utilized to compensate for process variations by supplementing the current drive of transistors used to precharge (PMOS) or discharge (NMOS) an output node of a secondary (e.g., inverter) stage of the buffer circuit.

公开(公告)号：DE102006001073A1

公开(公告)日：2006-07-20

申请号：DE102006001073

申请日：2006-01-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAN JONGHEE

IPC: G11C11/4076

Abstract: A duty cycle detector comprising a first circuit configured to receive clock cycles including a first level and a second level. The first circuit is configured to obtain a first value based on the length of the first level and to obtain second and third values based on the length of the second level. The first value is compared to the second and the third values to determine a duty cycle range of the clock cycles.

公开(公告)号：DE102004060578A1

公开(公告)日：2005-07-28

申请号：DE102004060578

申请日：2004-12-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAN JONGHEE ,  KIM JUNG PILL

IPC: H03B1/00 ,  H03K19/003 ,  H03K19/0185

公开(公告)号：DE102006011720A1

公开(公告)日：2006-11-09

申请号：DE102006011720

申请日：2006-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAN JONGHEE

IPC: G11C11/4093

Abstract: A circuit for latching data into a memory includes a receiver, a delay, and a selector. The receiver is configured for receiving a data signal, and the delay is configured to delay the data signal to provide a delayed data signal. The selector is configured to receive the delayed data signal, a data strobe signal, and an inverted data strobe signal and provide a first strobe signal and a second strobe signal in response to the delayed data signal, the data strobe signal, and the inverted data strobe signal. Rising edge data is latched into the memory in response to the first strobe signal and falling edge data is latched into the memory in response to the second strobe signal.

公开(公告)号：DE102004061299A1

公开(公告)日：2005-07-28

申请号：DE102004061299

申请日：2004-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAN JONGHEE

IPC: G11C7/10 ,  G11C11/4093

公开(公告)号：DE602004004533T2

公开(公告)日：2007-11-15

申请号：DE602004004533

申请日：2004-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAN JONGHEE ,  KIM PILL

IPC: H03L7/081 ,  H03K5/00 ,  H03K5/13 ,  H03L7/06

Abstract: Techniques and circuit configurations for fine phase adjustments, for example, in a delay-locked loop (DLL) circuit are provided. Multiple phase signals may be generated from a single current source by selectively coupling one or more delay elements to an output node of the current source. The delay elements may vary the timing of a signal generated by switching the current source.

公开(公告)号：DE102006022124A1

公开(公告)日：2007-02-22

申请号：DE102006022124

申请日：2006-05-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAN JONGHEE

IPC: G11C11/4093 ,  G06F13/38 ,  G11C7/10 ,  G11C11/4076

Abstract: An input circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal and a second signal and to sample the first signal via the second signal and provide signal samples of the first signal. The second circuit is configured to receive a third signal and the signal samples and to update a second circuit output signal via the third signal and provide the updated second circuit output signal. The third circuit is configured to receive a clock signal and the second signal and to provide the third signal. The third circuit is also configured to synchronize edges in the third signal to edges in the second signal and edges in the clock signal.

公开(公告)号：DE102006001082A1

公开(公告)日：2006-07-20

申请号：DE102006001082

申请日：2006-01-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAN JONGHEE ,  KIM JOONHO ,  KIM JUNG PILL

IPC: G11C7/22 ,  H03K5/156

Abstract: A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in response to charge flow that is regulated by the first circuit and the second circuit, wherein the first circuit is configured to receive a clock signal and change the charge flow at a first transition of the clock signal. The second circuit is configured to change the charge flow at a second transition of the clock signal. The first circuit and the second circuit are configured to change the charge flow in response to obtaining the threshold value.