公开(公告)号：DE69637697D1

公开(公告)日：2008-11-13

申请号：DE69637697

申请日：1996-08-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHWALKE UDO ,  HANSCH WILFRIED

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/8238

Abstract: A MOSFET device utilizes the gate depletion effect to reduce the oxide field over the junction area. Since the gate depletion effect is present in the non-conducting off state for n+ gate PMOS devices and p+ gate NMOS devices, performance degradation is overcome. The level of doping of the gate is critical. In order to prevent gate depletion in the conducting, on state, the NMOS FET must use a highly doped n+ gate. The PMOS FET n+ gate must be non-degeneratively doped in order to utilize the advantage of the gate depletion in the non-conducting, off state. This is accomplished by implanting different doses of the same dopant type into the different gates. The MOSFET device can be implemented equally well for n+ gate PMOS FET devices as well as for p+ gate NMOS FET devices.

公开(公告)号：DE69636244T2

公开(公告)日：2007-04-26

申请号：DE69636244

申请日：1996-12-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BRONNER GARY B ,  HANSCH WILFRIED ,  NOBLE WENDELL P

IPC: H01L21/8242 ,  H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L27/108

Abstract: A buried plate particularly suitable for formation of a common plate of a plurality of trench capacitors, such as are employed in dynamic random access memories, is formed by implantation of impurities in one or more regions of a wafer or semiconductor layer, epitaxially growing a layer of semiconductor material over the implanted regions and diffusing the implanted impurities into the wafer or semiconductor layer and into the epitaxial layer. Diffusion from such a source avoids process complexity compared with provision of diffusion sources within capacitor trenches and further provides an impurity concentration profile which varies with depth within the resulting body of semiconductor material, resulting in a well-defined boundary of the buried plate and an isolation region both above and below the buried plate. The structure allows biasing of the buried plate as desired, such as for reducing electrical stress on the capacitor dielectric to allow reduction in thickness thereof and reduction of area required for the trench capacitor.

公开(公告)号：DE69636244D1

公开(公告)日：2006-07-27

申请号：DE69636244

申请日：1996-12-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BRONNER GARY B ,  HANSCH WILFRIED ,  NOBLE WENDELL P

IPC: H01L21/8242 ,  H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L27/108

Abstract: A buried plate particularly suitable for formation of a common plate of a plurality of trench capacitors, such as are employed in dynamic random access memories, is formed by implantation of impurities in one or more regions of a wafer or semiconductor layer, epitaxially growing a layer of semiconductor material over the implanted regions and diffusing the implanted impurities into the wafer or semiconductor layer and into the epitaxial layer. Diffusion from such a source avoids process complexity compared with provision of diffusion sources within capacitor trenches and further provides an impurity concentration profile which varies with depth within the resulting body of semiconductor material, resulting in a well-defined boundary of the buried plate and an isolation region both above and below the buried plate. The structure allows biasing of the buried plate as desired, such as for reducing electrical stress on the capacitor dielectric to allow reduction in thickness thereof and reduction of area required for the trench capacitor.