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    4.
    发明专利
    未知

    公开(公告)号：DE69637697D1

    公开(公告)日：2008-11-13

    申请号：DE69637697

    申请日：1996-08-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHWALKE UDO ,  HANSCH WILFRIED

    IPC: H01L27/092 ,  H01L29/49 ,  H01L21/8238

    Abstract: A MOSFET device utilizes the gate depletion effect to reduce the oxide field over the junction area. Since the gate depletion effect is present in the non-conducting off state for n+ gate PMOS devices and p+ gate NMOS devices, performance degradation is overcome. The level of doping of the gate is critical. In order to prevent gate depletion in the conducting, on state, the NMOS FET must use a highly doped n+ gate. The PMOS FET n+ gate must be non-degeneratively doped in order to utilize the advantage of the gate depletion in the non-conducting, off state. This is accomplished by implanting different doses of the same dopant type into the different gates. The MOSFET device can be implemented equally well for n+ gate PMOS FET devices as well as for p+ gate NMOS FET devices.

    5.
    发明专利
    未知

    公开(公告)号：DE59410347D1

    公开(公告)日：2004-02-05

    申请号：DE59410347

    申请日：1994-10-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHWALKE UDO ,  STOISIEK MICHAEL

    IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/74 ,  H01L29/78

    Abstract: In an integrated circuit arrangement with at least one power component and low-voltage components, at least one power component is produced in a semiconductor substrate, at least one contact of the power component being arranged on a main surface of the substrate (1). The contact (11) is covered with an insulation layer (13), on the surface of which at least one thin-film component, in particular a thin-film transistor (14, 15, 16, 17, 18), is produced above the contact (11).

    6.
    发明专利
    未知

    公开(公告)号：DE59608080D1

    公开(公告)日：2001-12-06

    申请号：DE59608080

    申请日：1996-07-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHWALKE UDO ,  KERBER MARTIN

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

    Abstract: PCT No. PCT/DE96/01202 Sec. 371 Date Jan. 9, 1998 Sec. 102(e) Date Jan. 9, 1998 PCT Filed Jul. 4, 1996 PCT Pub. No. WO97/03462 PCT Pub. Date Jan. 30, 1997In the production of a dual work function CMOS circuit, a polysilicon layer is produced for the purpose of forming a gate structure, the average grain diameter of which polysilicon layer is greater than the minimum extent in the gate structure, in order to suppress lateral dopant diffusion. In particular, a constriction having a width less than the average grain diameter is produced in the gate structure.

    7.
    发明专利
    未知

    公开(公告)号：DE59607846D1

    公开(公告)日：2001-11-08

    申请号：DE59607846

    申请日：1996-11-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHWALKE UDO

    IPC: H01L29/40 ,  H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L29/786

    Abstract: PCT No. PCT/DE96/02121 Sec. 371 Date May 29, 1998 Sec. 102(e) Date May 29, 1998 PCT Filed Nov. 7, 1996 PCT Pub. No. WO97/20336 PCT Pub. Date Jun. 5, 1997In order to produce an MOS transistor in an SOI substrate, the silicon layer (3), a gate dielectric (4) and an electrode layer (5) are structured in MESA fashion to form an active region. The flanks of the MESA structure (7) are provided with insulating spacers (8). In a further structuring step, a gate electrode (12) is formed from the electrode layer (5). The process provides a high packing density and at the same time avoids the problem of gate side-wall control as well as premature breakdown at oxide edges.

    8.
    发明专利
    未知

    公开(公告)号：DE59812336D1

    公开(公告)日：2005-01-05

    申请号：DE59812336

    申请日：1998-05-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHWALKE UDO ,  LUDWIG BURKHARD

    IPC: H01L21/768 ,  H01L23/485

    Abstract: A doped region is provided on a substrate. A plane with conductive useful structures and a conductive filler structure is arranged at the surface of the substrate. The conductive filler structure is conductively connected to the doped region. In this way, charging of the conductive filler structure, which is provided for improving the planarity of the circuit arrangement and has no circuit-oriented function, is avoided.

    10.
    发明专利
    未知

    公开(公告)号：AT206558T

    公开(公告)日：2001-10-15

    申请号：AT96945866

    申请日：1996-11-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHWALKE UDO

    IPC: H01L29/40 ,  H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L29/786

    Abstract: PCT No. PCT/DE96/02121 Sec. 371 Date May 29, 1998 Sec. 102(e) Date May 29, 1998 PCT Filed Nov. 7, 1996 PCT Pub. No. WO97/20336 PCT Pub. Date Jun. 5, 1997In order to produce an MOS transistor in an SOI substrate, the silicon layer (3), a gate dielectric (4) and an electrode layer (5) are structured in MESA fashion to form an active region. The flanks of the MESA structure (7) are provided with insulating spacers (8). In a further structuring step, a gate electrode (12) is formed from the electrode layer (5). The process provides a high packing density and at the same time avoids the problem of gate side-wall control as well as premature breakdown at oxide edges.

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